• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Custom IC Design
  3. Manual editing of a p2lvsfile

Stats

  • Locked Locked
  • Replies 6
  • Subscribers 125
  • Views 7414
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Manual editing of a p2lvsfile

Slawa
Slawa over 15 years ago

 Hello

 After I have faced the following error: ERROR (LBMISC-215480): at "RCXdspf": LVS connectivity file /.../  is missing .2. in the course of start qrc at me there was a necessity of editing p2lvsfile.

In a "ICT.file" is
  # Diffusion Layers
diffusion NP {thickness, resistivity} and

 # dielectric Layers
dielectric   STI {conformal FALSE, height, thickness, dielectric_constant}.

How they are necessary for setting in p2lvsfile if to them as a matter of fact corresponds nothing in a RULEfile? 

 How to be with layers which are created directly in RULEfile but are used in LVSFILE? For example there is layer PACTIVE=Layer1 and (Layer2 or Layer3) which is set in RULEfile and in LVSFILE it is used only as:

 model = diode[DP],DP
element diode[DP] DPPLUS PACTIVE NWELL

 It turns out that in LVSFILE there is no information on the given layer as well as there is no information on it in ICT.

 

Best regards

Beginner engineer from Russia 

  • Cancel
Parents
  • Quek
    Quek over 15 years ago

    Hi Slawa

    I am also not sure about the cause of your compilation problem. Perhaps it would be good to get some help from Cadence support.

    You can map multiple lvs layers to a single process layer as follows:
    pro_layer=STI   ext_layer=nwell_conn,Nburied,psubstrate

    Some p2lvsfile features such as specification of rho, temperature coefficient, etc have been shifted to the ictfile because we now use ictfile for both cell and transistor level simulation. Since you are learning about Techgen and QRC, it would really be better if you can start with layer_setup file and not p2lvsfile. The lack of a semi-colon at the end of the line in layer_setup file is just one of the differences that it has with p2lvsfile.

    Best regards
    Quek

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Reply
  • Quek
    Quek over 15 years ago

    Hi Slawa

    I am also not sure about the cause of your compilation problem. Perhaps it would be good to get some help from Cadence support.

    You can map multiple lvs layers to a single process layer as follows:
    pro_layer=STI   ext_layer=nwell_conn,Nburied,psubstrate

    Some p2lvsfile features such as specification of rho, temperature coefficient, etc have been shifted to the ictfile because we now use ictfile for both cell and transistor level simulation. Since you are learning about Techgen and QRC, it would really be better if you can start with layer_setup file and not p2lvsfile. The lack of a semi-colon at the end of the line in layer_setup file is just one of the differences that it has with p2lvsfile.

    Best regards
    Quek

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information