assura lvs problem in ibm 90nm pdk

I uploaded them in   http://www.4shared.com/file/8sxfetCS/lvs_error2.html   and shall be very glad if you kindly comment on them.

Thank You .

Regards ....

The Assura317 log files that ran successfully indicated that you have filled up the lvs form as follows:

=== Layout ===
Library : components
Cell : components
View : layout

But the error message indicated that when you used Assura32, you are filling up the form like this:

=== Layout ===
Library : components
Cell : caps
View : layout

Would you please recheck again?

Best regards
Quek

=== From your rsf file ===
avParameters(
  ?inputLayout ( "df2" "components" )
  ?cellName "components"
  ?viewName "layout"

Thank you Quek for your keen observation. I have uploaded newer files in http://www.4shared.com/file/vbM3bfOl/lvs_errors3.html . My log files with assura317 are not latest, as can be seen there if the simulation dates are checked, because I can no longer complete the lvs with either version of assura. So, I picked the complete lvs log files from my previous records. The recent log files are same for both the versions.

Both the log files notes the names of the Layout and schematic cells, which is 'caps' everywhere.

One more observation is, the following warning comes twice in lvs_Errors_av32.log and once in lvs_Errors_av317.log, though I dont know whether it speaks something here.

Would you please try to dig something out of here?

Thank You Very Much...
Regards

Would you please upload the file "Ind_errors.sdb.ascii" after creating it using vldbToCdl in the Assura32 run directory:

terminal>vldbToCdl Ind_errors.sdb > Ind_errors.sdb.ascii

If the file Ind_errors.ldb is present, please also convert and upload it.

The warning message should not be related to the current problem. It is due to different behaviour between Assura and an older tool named Dracula. When Dracula reads in a cdl netlist that does not has *.BIPOLAR control cmd, it discards all analog devices (diodes, caps, resistors). Assura does not has this behaviour. The warning message can be ignored.

Best regards
Quek

Sorry for the delay. Today I could work in our lab (maintainance had been going on), collected the files and would like to upload them in http://www.4shared.com/file/N3ojOtv1/LVS_ASCIIs.html   .  I found the following information in 'Ind_Errors.sdb.ascii':

* "caps schematic components" renamed to    "capsschematiccomponents.0"
.subckt capsschematiccomponents.0 incap outcap gnd!

Is it renaming my schematic cell !!  It might be the problem if this is true. Would you please write me what could be the possible solution ?

Thank You,

Best Regards ...

Hi iamlearning

Thanks for the files. Yes, it is renaming your top cell. Currently your top schematic cellname is "caps" and you have also placed a cell named "caps" from another library. It looks like Assura32 does not allow the top cellname to be the same as a subcell name and hence automatically renamed it. Assura41 does not has this behaviour. I think your problem can be easily resolved by simply renaming your top cell from "caps" to some other name, e.g. "test_caps".

For sharing of log files, you can upload a file as follows:
a. After you have clicked on "Reply" button, notice that there are 4 tabs under the "Reply to an Existing Message" heading.
b. Click on the tab named "Options"
c. Click on "Add/Update" button for file attachment

Best regards
Quek

But, I dont have more than one cell named 'caps'. I would like to attach here the screenshot of my schematic view, where it is evident that, in is not inheriting anything other than the 'mimcap'.

However, today I could identify the problem luckily. I used to include the cdl netlist in the lvs form with assura317, but assura32 doesn't need it. I forgot to include it today in the lvs form of assura32 and the lvs was complete. These types of strange problems are difficult to identify and are much bothering.

Thank You, Quek for your helps :) .

Best Regards.

Thanks for the explanation. It does not matter whether the "caps" cell in the schematic vnl netlist comes from the actual schematic or an included netlist. There must be another cell named "caps" in your setup. Would you please check your included cdl netlist to see if it contains something similar to ".subckt caps"?

Thanks
Quek

I checked the cdl netlist. It has only one .subckt named 'caps'. I also checked the vnl netlists of the schematic and the layout and none of them have double 'caps'. The problem might be elsewhere.

Thank you.

Regards

Thanks for the check. Actually this is exactly the problem. I have already reproduced the behaviour using Assura41USR1_HF8. Previously I included a cell in the schematic that has the same name as the top cell and it did not create any problem. Now I include the cell through a cdl file and the problem appeared. My schematic top cell got renamed too and my lvs aborted with the same error as yours: