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some strange layout error

tester

Dear All,

The DRC test has been passed with no errors. However, there are a few area still have flashing x sign. For instance, the portion of metal 1 extended from the source of PMOS, which overlaps vdd (metal 1 as well) has flashing x sign. Can anyone give me some hint please?

Thanks

 

 

 

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  • tester

    Dear Andrew,

     I am very sorry for the extreme short post before. Here is the information that I found to the best of my knowledge. Please feel free to let me know if you need more information.

    I am using IC5.1.41 for schematic and the Virtuoso XL layout editor for drawing the layout. In addition, I am using Assura for the DRC checking. The design kit that I used is Jazz CA 18. The image is attached with this email and the error message after clicking the verify->marker is the following:

    Warning: Overlap between rectangular on layer "metal1 drawing' on net 'vdd!' and instance '|M6' with pin 'S' on the 'net 13' creates a short.

    Thanks.

    Note: the upper most top metal 1 is vdd and the net 13 is the metal 1 conntectted from the source of M6 to Vdd. M6 is the active device shown in the picture. The contact that I used from the nwell to vdd is "NTAP", which I am not very familiar with it.

    By the way, I tried to copy and paste the image but could not find it from the preview. Could you tell me how to post the image here? Thanks again.

        

     

     

Reply
  • tester

    Dear Andrew,

     I am very sorry for the extreme short post before. Here is the information that I found to the best of my knowledge. Please feel free to let me know if you need more information.

    I am using IC5.1.41 for schematic and the Virtuoso XL layout editor for drawing the layout. In addition, I am using Assura for the DRC checking. The design kit that I used is Jazz CA 18. The image is attached with this email and the error message after clicking the verify->marker is the following:

    Warning: Overlap between rectangular on layer "metal1 drawing' on net 'vdd!' and instance '|M6' with pin 'S' on the 'net 13' creates a short.

    Thanks.

    Note: the upper most top metal 1 is vdd and the net 13 is the metal 1 conntectted from the source of M6 to Vdd. M6 is the active device shown in the picture. The contact that I used from the nwell to vdd is "NTAP", which I am not very familiar with it.

    By the way, I tried to copy and paste the image but could not find it from the preview. Could you tell me how to post the image here? Thanks again.

        

     

     

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