The DRC test has been passed with no errors. However, there are a few area still have flashing x sign. For instance, the portion of metal 1 extended from the source of PMOS, which overlaps vdd (metal 1 as well) has flashing x sign. Can anyone give me some hint please?
I hope you don't think I'm being rude, but how do you think anyone could possibly answer your question? You didn't say:
That's just the bare minimum. Ideally a picture of the problem would help. Did you use Layout XL to do the layout? Maybe there's a marker on the layout due to layout XL? Perhaps you can do Verify->Explain and click on the marker to see if there's an explanation?
I am very sorry for the extreme short post before. Here is the information that I found to the best of my knowledge. Please feel free to let me know if you need more information.
I am using IC5.1.41 for schematic and the Virtuoso XL layout editor for drawing the layout. In addition, I am using Assura for the DRC checking. The design kit that I used is Jazz CA 18. The image is attached with this email and the error message after clicking the verify->marker is the following:
Warning: Overlap between rectangular on layer "metal1 drawing' on net 'vdd!' and instance '|M6' with pin 'S' on the 'net 13' creates a short.
Note: the upper most top metal 1 is vdd and the net 13 is the metal 1 conntectted from the source of M6 to Vdd. M6 is the active device shown in the picture. The contact that I used from the nwell to vdd is "NTAP", which I am not very familiar with it.
By the way, I tried to copy and paste the image but could not find it from the preview. Could you tell me how to post the image here? Thanks again.
I thought I'd answered this, but couldn't see it. Anyway, the message you're getting is almost certainly from Layout XL. Did you try running LVS - DRC wouldn't show the error.
Anyway, to upload the picture, hit the Reply button (not the quick reply) and then go onto the Options tab which gives you the ability to upload an attachment.
With your hints in the previous posting and this one, I have already figured out the issue. Thank you again for your great support.
Sorry for bothering you again since the error message came out again. What I did previously is to remove an extra metal 1 layer above the gate area, and the error message was gone. However, when I login today, the error message is still there. I have attached the figure this time and hope that helps a little bit.
In my systerm, there are two places that I can run DRC. One is "assura->DRC" and the other is "verify->DRC". I could not find "LVS->DRC". The "assura->DRC" works for me (but with the waring marker as you can see in the attached file). However, when I tried "verify->DRC", it shows that "failed to find DRC rules divaDRC.rul in library ca 18".