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some strange layout error

tester

Dear All,

The DRC test has been passed with no errors. However, there are a few area still have flashing x sign. For instance, the portion of metal 1 extended from the source of PMOS, which overlaps vdd (metal 1 as well) has flashing x sign. Can anyone give me some hint please?

Thanks

 

 

 

Parents

  • Dear Andrew,

    Sorry for bothering you again since the error message came out again. What I did previously is to remove an extra metal 1 layer above the gate area, and the error message was gone. However, when I login today, the error message is still there. I have attached the figure this time and hope that helps a little bit.

    In my systerm, there are two places that I can run DRC. One is "assura->DRC" and the other is "verify->DRC". I could not find "LVS->DRC". The "assura->DRC" works for me (but with the waring marker as you can see in the attached file). However, when I tried "verify->DRC", it shows that "failed to find DRC rules divaDRC.rul in library ca 18".

    Thanks

     

Reply

  • Dear Andrew,

    Sorry for bothering you again since the error message came out again. What I did previously is to remove an extra metal 1 layer above the gate area, and the error message was gone. However, when I login today, the error message is still there. I have attached the figure this time and hope that helps a little bit.

    In my systerm, there are two places that I can run DRC. One is "assura->DRC" and the other is "verify->DRC". I could not find "LVS->DRC". The "assura->DRC" works for me (but with the waring marker as you can see in the attached file). However, when I tried "verify->DRC", it shows that "failed to find DRC rules divaDRC.rul in library ca 18".

    Thanks

     

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