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  3. Module instantiation using Generate statement

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Module instantiation using Generate statement

write2rammy
write2rammy over 15 years ago

Hi all,

     I am using a generate statement to instantiate a delay module (cur_starved_delay) 11 times. The basic idea is to model a 11 stage ring oscillator using current starved delay cell. But i get syntax error in generate statement. Can anyone help me with this. The code is attached below.

 

module multiphase_vco(Vbias_p,Vbias_n,Vdd,Vss, out);
parameter integer NO_STAGE  = 11;
parameter real C_load = 1e-12;
parameter real Kp = 1;
parameter real Kn = 1;
parameter real Vt = 0.2;
parameter real pos_tol = 0.2;
parameter real neg_tol = -0.2;

genvar i;

input Vbias_p,Vbias_n,Vdd,Vss;
output [11-1:0] out;

voltage Vbias_p,Vbias_n,Vdd,Vss;
electrical [NO_STAGE-1:0] out;
real ph_out[NO_STAGE-1:0];


generate
    for (i =1;i<=11;i=i+1) begin
          cur_starved_delay #(.C_load(C_load),.Kp(Kp),.Kn(Kn),.Vt(Vt),.pos_tol(pos_tol),.neg_tol(neg_tol))
                 D_i(.Vin(ph_out[i-1]),.Vbias_p(Vbias_p),.Vbias_n(Vbias_n),.Vdd(Vdd),.Vss(Vss),.Vout(ph_out[i]));
    end
endgenerate

ph_out[0] = ph_out[NO_STAGE]);

@(initial_step) begin
    ph_out[0] = V(Vss);
end
end    

endmodule

 

 

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  • write2rammy
    write2rammy over 15 years ago

     Please ignore the extra end statement after initial_step block

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  • write2rammy
    write2rammy over 15 years ago

     Please ignore the extra end statement after initial_step block

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