how to use "delete cell" or any block syntax to let Assura ignore bit cell?

Hi Julia

I will interprete "It is not a standard logic device" to mean that your current Assura extract rules file does not has the cmds to extract the special devices in the memory block. This would be a limitation of the foundry rules file and not Assura itself. If you use ?ignoreCell from avParameters to prevent extraction of this cell, will it work? You can apply avCompareRules "ignoreCell" to also ignore the same cell on schematic side.

If the above does not work, please check the log file for any warnings/errors on why the cmds did not work. Thanks.

Best regards
Quek

Hi, Quek

Thanks for your reply.

I just tried this "ignoreCell" and those pin mismatch errors for the dummy cells in memory block  were gone; but what do you mean " also ignore the same cell on schematic side"? I didn't do anything in the schematic;

 Now I have other error messages :

there is Pins mismatch for the top level; there are rewires, nets, devices mismatch for the memory block...; Actually this whole block ( top _ level ) is Calibre lvs clean?  so I don't what to do to make Assura LVS clean.

Hopefully you can give me more suggestions. Thanks

Julia

Hi Julia

If you use ?ignoreCell cmd from avParameters section, you will ignore the cell for layout extraction. If you would like to include the cell in lvs database for subsequent parasitic extraction using QRC but want to ignore it for comparison, then you can use ignoreCell from avCompareRules. E.g.

avCompareRules(
   schematic( ignoreCell( cell("myBitCell") ) )
   layout( ignoreCell( cell("myBitCell") ) )
)

The above cmd ignores the bit cell in both schematic and layout.

Unless it is for a very simple cell, it is never an easy process to match the lvs results of a tool to that of another tool. This is due to the different rules used by both tools (e.g. different ways of identifying pins, etc). An easy way for you to duplicate Calibre results is to simply use PVS instead of Assura. PVS can read in Calibre rules as it is.

You can try the following Assura cmds:
a. Use pinTextFile to add top level pins to resolve the pin mismatches. But look at the erc file first to check if there are any reasons why existing pins (if any) are not captured. Perhaps it is simply due to some typo in textToPin cmds in the extract rules file.

b. Use expandOnError cmd to automatically promote cells if there are pin, device count, parameter, etc mismatches.

c. Check for possible missing cell bindings and add bind cmds if necessary.

d. My preference is to always start with "device" errors because most of the time, resolving the device errors would also resolve the net errors.

Best regards
Quek