Stats

  • Locked Locked
  • Replies 3
  • Subscribers 126
  • Views 2472
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

how to use "delete cell" or any block syntax to let Assura ignore bit cell?

lijulia

We used faraday memory compiler to generate memory cell .gds file and stream in to the Cadence, but got Assura LVS errors when we did chip  top level lvs check,and most issues related to the dummy cells in the memory block, eg. SHLD_DMY_CORNER_SE cell;

 And we got this reply from the faraday "Since the bit cell using special design rule.  It is not a standard logic device. your error is caused by Assura LVS command file. As you know , our memory was pass CALIBRE DRC/LVS ,and has good yield in silicon. Our suggestion is not to check the bit cell by using Assura DRC/LVS.The memory bit cell was provided by foundry , UMC and Faraday will insure the bit cell was correct. Please ignore all bit cell error when you running DRC/LVS (maybe use "delete cell" or any block syntax to let Assura ignore bit cell) "

 

But I already tried ignore cells, blackbox etc.; but nothing work; after I flatten the whole top, it didn't complain the pin mismatch of the dummy cells but got other errors...

 

Please give me some suggestion about this, thanks

 

 


Parents

  • Hi, Quek

    Thanks for your reply.

    I just tried this "ignoreCell" and those pin mismatch errors for the dummy cells in memory block  were gone; but what do you mean " also ignore the same cell on schematic side"? I didn't do anything in the schematic;

     Now I have other error messages :

    there is Pins mismatch for the top level; there are rewires, nets, devices mismatch for the memory block...; Actually this whole block ( top _ level ) is Calibre lvs clean?  so I don't what to do to make Assura LVS clean.

     

    Hopefully you can give me more suggestions. Thanks

     

    Julia

     

     

     

     

Reply

  • Hi, Quek

    Thanks for your reply.

    I just tried this "ignoreCell" and those pin mismatch errors for the dummy cells in memory block  were gone; but what do you mean " also ignore the same cell on schematic side"? I didn't do anything in the schematic;

     Now I have other error messages :

    there is Pins mismatch for the top level; there are rewires, nets, devices mismatch for the memory block...; Actually this whole block ( top _ level ) is Calibre lvs clean?  so I don't what to do to make Assura LVS clean.

     

    Hopefully you can give me more suggestions. Thanks

     

    Julia

     

     

     

     

Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.