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change the name of a net in virtuoso XL

tester

Dear All,

I am using ic 5.1.41 for schematic and the associated virtuoso XL for layout drawing. I have a very simple question? how do I change the name of a net?

Thanks

 

 

Parents

  • Dear Andrew,

    Thank you very much for your reply, and here is the delimma that I am having:

    The problem that I am having is the net for vdd. I created a rectangular in metal 1 and wanted to be vdd. (I checked the property righer after the creation and it shows as net 13). Later, I created a pin with a name of "vdd!" in metal 1 and put it on top of net 13. Then I got an error messge stating that there is short between "net13" and "vdd!". Orignally, I thought to force the change of "net13" to "vdd!" since in the schematic, it has "vdd!" already. Now, it seems that I need somehow generate it from schematic. The only thing that I know is to use "generate from the source", which will override all the stuff that I have earlier, which I do not want to erase all of the work previously. I was wondering whether there is a way to just generate the protion of the interested from the schematic as needed. In this case, just the "vdd!" net and all the rest remain untouched.

    Thanks

     

     

Reply

  • Dear Andrew,

    Thank you very much for your reply, and here is the delimma that I am having:

    The problem that I am having is the net for vdd. I created a rectangular in metal 1 and wanted to be vdd. (I checked the property righer after the creation and it shows as net 13). Later, I created a pin with a name of "vdd!" in metal 1 and put it on top of net 13. Then I got an error messge stating that there is short between "net13" and "vdd!". Orignally, I thought to force the change of "net13" to "vdd!" since in the schematic, it has "vdd!" already. Now, it seems that I need somehow generate it from schematic. The only thing that I know is to use "generate from the source", which will override all the stuff that I have earlier, which I do not want to erase all of the work previously. I was wondering whether there is a way to just generate the protion of the interested from the schematic as needed. In this case, just the "vdd!" net and all the rest remain untouched.

    Thanks

     

     

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