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How to build a standard cell model (for a printed transistor) in Cadence

Hallo,

I have the model equations for a printed transistor (Quite different from BSIM3 and EKV models). Now I need to use this model in Cadence to simulate circuits. So when I place a nmos the simulator should use this model instead of BSIM3 or EKV.. I guess I can't model this using Verilog-A because I am not intending to do a behavioral modelling.

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write2rammy over 15 years ago

Hi Andrew,
Sorry for the confusion. I have to write the models either in verilog-A or spice. My question is if I write the model in spice and use in cadence, will it be faster than the verilog-A model?
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write2rammy over 15 years ago

Hi Andrew,
Sorry for the confusion. I have to write the models either in verilog-A or spice. My question is if I write the model in spice and use in cadence, will it be faster than the verilog-A model?
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