How to build a standard cell model (for a printed transistor) in Cadence

Why can't you use VerilogA for this? This is comething that VerilogA is being increasingly used for - at least for initial implementation of compact device models.

To get you started with VerilogA modelling of devices, I'd first of all advise putting this library in your cds.lib and looking at some examples:

ahdlLib         $(inst_root_with:tools/dfII/bin/icfb)/tools/dfII/samples/artist/ahdlLib

Within ahdlLib you'll see several cells with veriloga views:

mos_tft - a thin film transistor model
mos_level1 - a level1 MOS model
n_jfet - a jfet model.

If you want to see some more modern, (and more complex) device models in VerilogA, see
http://www.nxp.com/models/mos_models/psp/ which covers the NXP/Penn State "PSP" model. In fact you might find it easier to look here: http://pspmodel.asu.edu/

There are a few other places around that might be useful:

http://www.bmas-conf.org/2008/2-3_Paper.pdf
http://www.designers-guide.org/VerilogAMS/ - a collection of models, including links to the EKV model implemented in VerilogA.

As for books on VerilogA and modelling:

http://www.designers-guide.org/Books/#Kundert-2004
http://www.springerlink.com/content/k72461p50036466p/

The first is a good coverage of the language - the second looks as if it is specifically aimed at people writing transistor models (I have the first book, but not the second).

Here's another example:

http://www.designers-guide.org/Forum/YaBB.pl?num=1268789424

The alternative is that it's possible to implement the model using the C model interface into spectre, but this normally would need epecialist assistance (we do not provide documentation for doing this out of the box). Please contact your account manager or customer support if you want to pursue that route. It's not for the faint hearted and normally would be used only if you have a very large number of instances that will be used, and have detailed experience of device modelling in simulators.

Regards,

Andrew.

 Andrew,

           Thank you for your prompt reply. I will try doing it with Verilog-A. But can you explain the problems with using Verilog-A models for a large number of instantiations (mentioned in the last para of your reply).

Whilst we've done a lot of optimization for VerilogA models representing compact device models, typically I wouldn't expect them to be as fast as a model written in C. I recall seeing figures of a factor of 2 speed difference (although your mileage may vary), and it depends on the number of other devices in the circuit, and so on (and very much on how well the model is written).

So my point was that if you have a very large number of devices (tens of thousands, say, or more), then you may need the performance improvement gained by writing in C. However, we do have some large customers that have their own transistor models (e.g. variants of bsim3v3) and use these all the time.

Regards,

Andrew.

 Andrew,

          Thank you for your reply. Also I found in the following links, an alternate method using a spectre or spice netlist.

http://www.cadence.com/community/forums/T/14736.aspx 

http://www.cadence.com/Community/blogs/rf/archive/2009/01/07/tip-of-the-week-how-to-simulate-a-subcircuit-netlist-with-spectre-in-ade.aspx

http://www.designers-guide.org/Forum/YaBB.pl?num=1191334088

        So, if I do a spice model, convert it to spectre model and then use it, will it give better speed than a verilog-A models.

 Sorry. The second link is incomplete. I have added the right one below.

http://www.cadence.com/Community/blogs/rf/archive/2009/01/07/tip-of-the-week-how-to-simulate-a-subcircuit-netlist-with-spectre-in-ade.aspx 

Now I'm confused. If you have a SPICE model file, you can use that directly in spectre (no need to translate the format as spectre can read SPICE syntax directly).

I thought you said you had a set of equations - if so, that's not a SPICE model file. Iwas suggesting a solution to implement a model using that set of equations.

Regards,

Andrew.

 Hi Andrew,

         Sorry for the confusion. I have to write the models either in verilog-A or spice. My question is if I write the model in spice and use in cadence, will it be faster than the verilog-A model?

You're comparing Apples and Pears here. A SPICE model normally is referencing a built-in device model and just setting a set of parameters for that device model (e.g. setting the parameters for bsim3v3, bsim4, ekv, psp etc). Maybe a few parasitic devices around the device. A VerilogA model is a set of simultaneous differential equations (and some procedural code) which need to be solved. 

Provided the SPICE subckt model is not too complicated, it will probably be quicker to simulate. But impossible to give you a definite answer without knowing more.

Andrew.

 I thought I could write a standalone model using .SUBCKT and .ENDS. Now I understand your point.Thank you. So I will stick with verilog-A