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How to build a standard cell model (for a printed transistor) in Cadence

write2rammy

Hallo,

        I have the model equations for a printed transistor (Quite different from BSIM3 and EKV models). Now I need to use this model in Cadence to simulate circuits. So when I place a nmos the simulator should use this model instead of BSIM3 or EKV.. I guess I can't model this using Verilog-A because I am not intending to do a behavioral modelling.

Parents

  • You're comparing Apples and Pears here. A SPICE model normally is referencing a built-in device model and just setting a set of parameters for that device model (e.g. setting the parameters for bsim3v3, bsim4, ekv, psp etc). Maybe a few parasitic devices around the device. A VerilogA model is a set of simultaneous differential equations (and some procedural code) which need to be solved. 

    Provided the SPICE subckt model is not too complicated, it will probably be quicker to simulate. But impossible to give you a definite answer without knowing more.

    Andrew.

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  • You're comparing Apples and Pears here. A SPICE model normally is referencing a built-in device model and just setting a set of parameters for that device model (e.g. setting the parameters for bsim3v3, bsim4, ekv, psp etc). Maybe a few parasitic devices around the device. A VerilogA model is a set of simultaneous differential equations (and some procedural code) which need to be solved. 

    Provided the SPICE subckt model is not too complicated, it will probably be quicker to simulate. But impossible to give you a definite answer without knowing more.

    Andrew.

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