I will try to describe my problem the better i can.I have an op-amp
design that consists of several cells (main opamp,gain
boosters,cmfb,biasing).I have created the layout of all the above cells
and i pass successfully from DRC and LVS runs (clean runs,no errors no
warnings).The last step is to perform the parasitics' extraction and
run post layout simulations.Well,here things become a little bit
strange...Before i describe my problem in depth i must say that my
design kit is IBM's cms9flp and the versions of cadence virtuoso and assura are IC220.127.116.110.13 and 3.2_USR2_HF11 respectively.
I run LVS for each cell successfully (clean results) and then i run
successfully as well the assura QRC run (no errors-no warnings) for all
my cells and the result is the well known message of assura with the
av_extracted view's name and location in the library.
Next step is to simulate the av_extracted views.For this i create a
schematic with all the above cells interconnected as symbols and i use
the av_extracted declaration under Environment submenu of ADE L.
I run DC analysis at first and here is my issue.The currents in all
branches of the circuit are far away from the designed values.From a
quick thought you can say that i made mistake in transistor sizes
during layout but this should be reported by LVS but in any case i
double checked this by myself to be absolutely certain.Second thought
is that i have not calculated correct the widths of all metals that
make the interconnections in the design,i double checked this as well
according to pdk's rules for metals and viases.With a more careful view
in the values of the currents that dc analysis resulted i noticed that
all of them are divided by the product (m*nf),where m is multiplicity
and nf number of fingers!Looking at the vdd symbol i see that my
circuit consumes X mA but if i add all the currents from the subcells i
do not ever reach X/4 mA,so i ask myself where is the rest of the
current consumed?!Another strange thing is that even though that all
currents are wrong calculated the biasing voltages from the current
mirrors are exact to the design values...
Has anybody else come up with such an issue with this or another IBM's
pdk??Do you think that i should report this straightly in IBM's
Thanks in advance for any helpful answer.
PS. It is urgent for me since tape out date is close!!
Hi jimitoIf you simulate just a small cell (e.g. a current mirror block), do you have the same problem?Best regardsQuek
It seems that the circuit "burns" the desired value of total current
(the same with the value i get when i simulate the schematic with the
symbols not as av_extracted views but as schematic views) but when i add
all currents "by hand" from all branches i am far away from this
annotated value on the VDD symbol of schematics L.After some observation
on the annotated values i noticed that the indicated current on the
schematics L after the dc analysis is the current that flows into the
one finger of a transistor even if it has multiplicity factor (bus more
exactly) or not,that's why i wrote in my previous post that all values
are divided by the product (m*nf).
On the other hand,i simulated a test case with the main opamp only and
biases from ideal sources and an ideal cmfb circuit that i have created
and the problem still remains when av_extracted view is the simulated...
Another colleague that works in my lab a few months ago had created a test case with a simple resistively loaded common source topology and we tested my problem on it and it was simulated correctly after the RC extraction.We just divided the transistor into 2 parallel fets with bus and some fingers and connected it with the resistor with metal1 just to make the test,not anything important from layout aspect!
Do you suspect something that causes this strange problem or you think that IBM will give the answer?
Thanks a lot in advance.
Hi JimitoSorry for the late reply. Actually I think this looks like a setup issue that might has a reasonable explanation if there is a testcase. It would be good for your Prof to help contact Cadence or IBM support for this issue.Best regardsQuek
Well we contacted IBM and they admitted that there is an error while the total current is calculated when the av_extracted view is post simulated.They didn't give us any solution instead of proposing us to change all fets from my design to nfet_rf and pfet_rf (now i use the regular fets-nfet,pfet and the respective lvt versions)...Only in this case they said that the problem is solved...Anyway,this is the least annoying since if i multiply the multiplicity factor with the number of fingers and the simulation current i get the total correct current that i expected.So,i suppose that i am ok with it.But...
There is another more difficult issue that hasn't been solved up to now even from IBM's support (they proposed me the same solution i wrote above for this issue as well !!).After simulating my opamp i notice severe voltage mismatches at various symmetrical branches (20mV the one and 700mV for example the other !!!).We checked the layout with my professor and he admitted as well that everything is ok and that those mismatches cannot be explained...We made all the checks (parasitic resistances,widh of interconnection cables,symmetries,distances etc...) that must be done and we didn't find any problem to my layout.My professor insists that i must change all fets to RF fets for a cell and post simulate it,if problem still exists then he says that we must report back to IBM.This is a little bit difficult to be done.Have you ever seen something like that happening during post simulation with a specific design kit and in this case what did you do to solve it??
Thanks in advance,
Hi JimitoJust to be sure that those voltage mismatches are not due to a bad extracted view, you can try the following:a. In the terminal window, enter the following:terminal>setenv DBGRCX_CONNECTIVITY Yterminal>icfb &b. Run Assura LVS and QRC extraction to generate an rc extracted_viewAt the end of the extraction, there should be connectivity checking using gemini checker. This is to confirm that the netlist is still correct after insertion of rc parasitics.There are indeed some old cases in which we see bad simulation results due to broken nets in the extracted view. I think sending a testcase to IBM would be a good idea.Best regardsQuek