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IBM cms9flp & Assura QRC strange problem

jimito13

Hello all,

I will try to describe my problem the better i can.I have an op-amp design that consists of several cells (main opamp,gain boosters,cmfb,biasing).I have created the layout of all the above cells and i pass successfully from DRC and LVS runs (clean runs,no errors no warnings).The last step is to perform the parasitics' extraction and run post layout simulations.Well,here things become a little bit strange...Before i describe my problem in depth i must say that my design kit is IBM's cms9flp and the versions of cadence virtuoso and assura are IC6.1.3.500.13 and 3.2_USR2_HF11 respectively.

I run LVS for each cell successfully (clean results) and then i run successfully as well the assura QRC run (no errors-no warnings) for all my cells and the result is the well known message of assura with the av_extracted view's name and location in the library.

Next step is to simulate the av_extracted views.For this i create a schematic with all the above cells interconnected as symbols and i use the av_extracted declaration under Environment submenu of ADE L.

I run DC analysis at first and here is my issue.The currents in all branches of the circuit are far away from the designed values.From a quick thought you can say that i made mistake in transistor sizes during layout but this should be reported by LVS but in any case i double checked this by myself to be absolutely certain.Second thought is that i have not calculated correct the widths of all metals that make the interconnections in the design,i double checked this as well according to pdk's rules for metals and viases.With a more careful view in the values of the currents that dc analysis resulted i noticed that all of them are divided by the product (m*nf),where m is multiplicity and nf number of fingers!Looking at the vdd symbol i see that my circuit consumes X mA but if i add all the currents from the subcells i do not ever reach X/4 mA,so i ask myself where is the rest of the current consumed?!Another strange thing is that even though that all currents are wrong calculated the biasing voltages from the current mirrors are exact to the design values...

Has anybody else come up with such an issue with this or another IBM's pdk??Do you think that i should report this straightly in IBM's support??


Thanks in advance for any helpful answer.


PS. It is urgent for me since tape out date is close!!

Parents

  •  

    Hello Quek,

    It seems that the circuit "burns" the desired value of total current (the same with the value i get when i simulate the schematic with the symbols not as av_extracted views but as schematic views) but when i add all currents "by hand" from all branches i am far away from this annotated value on the VDD symbol of schematics L.After some observation on the annotated values i noticed that the indicated current on the schematics L after the dc analysis is the current that flows into the one finger of a transistor even if it has multiplicity factor (bus more exactly) or not,that's why i wrote in my previous post that all values are divided by the product (m*nf).

    On the other hand,i simulated a test case with the main opamp only and biases from ideal sources and an ideal cmfb circuit that i have created and the problem still remains when av_extracted view is the simulated...

    Another colleague that works in my lab a few months ago had created a test case with a simple resistively loaded common source topology and we tested my problem on it and it was simulated correctly after the RC extraction.We just divided the transistor into 2 parallel fets with bus and some fingers and connected it with the resistor with metal1 just to make the test,not anything important from layout aspect!

    Do you suspect something that causes this strange problem or you think that IBM will give the answer?

    Thanks a lot in advance.

    Regards,
    Jimito13

Reply

  •  

    Hello Quek,

    It seems that the circuit "burns" the desired value of total current (the same with the value i get when i simulate the schematic with the symbols not as av_extracted views but as schematic views) but when i add all currents "by hand" from all branches i am far away from this annotated value on the VDD symbol of schematics L.After some observation on the annotated values i noticed that the indicated current on the schematics L after the dc analysis is the current that flows into the one finger of a transistor even if it has multiplicity factor (bus more exactly) or not,that's why i wrote in my previous post that all values are divided by the product (m*nf).

    On the other hand,i simulated a test case with the main opamp only and biases from ideal sources and an ideal cmfb circuit that i have created and the problem still remains when av_extracted view is the simulated...

    Another colleague that works in my lab a few months ago had created a test case with a simple resistively loaded common source topology and we tested my problem on it and it was simulated correctly after the RC extraction.We just divided the transistor into 2 parallel fets with bus and some fingers and connected it with the resistor with metal1 just to make the test,not anything important from layout aspect!

    Do you suspect something that causes this strange problem or you think that IBM will give the answer?

    Thanks a lot in advance.

    Regards,
    Jimito13

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