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  3. mixed signal design flow

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mixed signal design flow

hon cheong
hon cheong over 15 years ago

Hi ,

I would like to know about the correct flow for mixed signal design. Assuming now I have all my analog blocks readily verified in spectre, and the layout of the analog blocks pass DRC and LVS check. My digital blocks ( e.g state machine) layout are obtained from the place and route tool ( Cadence encounter). If I want to verify the system which consist of both analog and digital circuits, should I stream out the digital blocks layout into Cadence Virtuoso to combine both digital and analog layout together, then run DRC and LVS again, and extract the parasitic and rerun the whole system simulation ? But I am wondering will it take me a very long time to run the simulation as the digital blocks might consist of quite a number of gates.

 I have run AMS simulation by combining the analog blocks and VHDL code together. But I am not convinced by the simulation result as the behavioral VHDL code and the analog circuits does not seems represent the actual circuit behavior after laid out ( parasitic, fan out effect etc).

 Please advice.

Thanks in advance.

 

Regards,

hon cheong

 

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  • hon cheong
    hon cheong over 14 years ago

    Hi Quek,

    Thanks for the reply.

    However, I am informed by MOSIS that no GDS file would be provided. Some of my colleague who done full digital design tape out their chip without the standard cell GDS file, in which the standard cell GDS file would be inserted during fabrication.

    Is that a way to verify my final circuit even without standard cell GDS file? Such as stream out the digital layout in other format? e.g DEF? I am not familiar with the streaming out methods available.

    Thank You.

    Regards,

    hon cheong

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  • hon cheong
    hon cheong over 14 years ago

    Hi Quek,

    Thanks for the reply.

    However, I am informed by MOSIS that no GDS file would be provided. Some of my colleague who done full digital design tape out their chip without the standard cell GDS file, in which the standard cell GDS file would be inserted during fabrication.

    Is that a way to verify my final circuit even without standard cell GDS file? Such as stream out the digital layout in other format? e.g DEF? I am not familiar with the streaming out methods available.

    Thank You.

    Regards,

    hon cheong

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