I would like to know about the correct flow for mixed signal design. Assuming now I have all my analog blocks readily verified in spectre, and the layout of the analog blocks pass DRC and LVS check. My digital blocks ( e.g state machine) layout are obtained from the place and route tool ( Cadence encounter). If I want to verify the system which consist of both analog and digital circuits, should I stream out the digital blocks layout into Cadence Virtuoso to combine both digital and analog layout together, then run DRC and LVS again, and extract the parasitic and rerun the whole system simulation ? But I am wondering will it take me a very long time to run the simulation as the digital blocks might consist of quite a number of gates.
I have run AMS simulation by combining the analog blocks and VHDL code together. But I am not convinced by the simulation result as the behavioral VHDL code and the analog circuits does not seems represent the actual circuit behavior after laid out ( parasitic, fan out effect etc).
Thanks in advance.
Hi hon cheongYour flow is correct. It is actually quite common to perform final integration on Virtuoso platform using gds from P&R tool. For such simulations, we can use fastspice simulator ultrasim. Ultrasim also has parasitic reduction feature to further reduce simulation time. You can of course also do parasitic reduction during QRC extraction.Best regardsQuek
Thanks for the useful information.
I have another issue regading the mixed signal design flow. Currently I am in a university, and access the IBM 130nm process through MOSIS. The standard cell GDS file is not provided by ARM. Is it possible to integrate both analog and digital layout together without the standard cell GDS file? I think it would be impossible for me to do DRC and LVS check without GDS file, is that true?
Thank You .
Hi hon cheongIt is indeed not possible to do drc and lvs check without the standard cell gds.You need the gds file. Integrating with standard cell gds would be quite meaningless because the gds file from the P&R tool would give lots of missing cell errors when imported into Virtuoso.Best regardsQuek
Thanks for the reply.
However, I am informed by MOSIS that no GDS file would be provided. Some of my colleague who done full digital design tape out their chip without the standard cell GDS file, in which the standard cell GDS file would be inserted during fabrication.
Is that a way to verify my final circuit even without standard cell GDS file? Such as stream out the digital layout in other format? e.g DEF? I am not familiar with the streaming out methods available.
Hi hon cheongWithout the standard cell gds, you will have the make the assumption that the tech lef which you have used for routing in the P&R tool is in sync with the drc rules file. Any placement errors that might result in metal spacing violations would not be detected if drc is only run on the interconnects. A full lvs check would not be possible. You can however define the digital cell as a blackbox and do lvs on analog portion and interface of analog/digital cells. Just stream out the digital design and stream it into Virtuoso. Then remove the internal parts of the digital cell, leaving only the pins.Best regardsQuek