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mixed signal design flow

hon cheong

Hi ,

I would like to know about the correct flow for mixed signal design. Assuming now I have all my analog blocks readily verified in spectre, and the layout of the analog blocks pass DRC and LVS check. My digital blocks ( e.g state machine) layout are obtained from the place and route tool ( Cadence encounter). If I want to verify the system which consist of both analog and digital circuits, should I stream out the digital blocks layout into Cadence Virtuoso to combine both digital and analog layout together, then run DRC and LVS again, and extract the parasitic and rerun the whole system simulation ? But I am wondering will it take me a very long time to run the simulation as the digital blocks might consist of quite a number of gates.

 I have run AMS simulation by combining the analog blocks and VHDL code together. But I am not convinced by the simulation result as the behavioral VHDL code and the analog circuits does not seems represent the actual circuit behavior after laid out ( parasitic, fan out effect etc).

 Please advice.

Thanks in advance.

 

Regards,

hon cheong

 

Parents

  • Hi all, 

    I'm also working along the same lines, and have two questions regarding simulation with this kind of mixed-signal flow. Lucky for me, I have access to the gds files, so I can run DRC and LVS on my full design in virtuoso. So no problem there. However, I'm hoping to use sdf back-annotation for digital cells and full spectre analog models for the rest. I've managed to do this in another technology node with Diva and the pearl mixed-extract flow, with everything running through spectreVerilog.

    The catch is this : we don't have the DRC/LVS/Parasite extract rules for Diva or Assura.  We have to use a 3rd party tool. It works well, and I can get standard parasitic formats (SPEF, DSPF, HSPICE), seperated in hierarchical sections if I want (ie, analog-only). So I thought about importing the SPEF in Encounter (with analog blocks as black boxes), and then get my .sdf file from there. I found the box where to tell AMS about the sdf file, too.  But I'm stuck on how to pass the parasitic netlist to AMS for the analog blocks. I know that UltraSIM can attach DSPF files, but what about Spectre or APS? I've tried to look around the web, manuals and Cadence support, but nothing yet.

    My second question is about .sdf generation in Encounter. I have done it before in version 8.1, and it worked great with the spectreVerilog, AMS and another 3rd party simulator. However, the same design produces a quite different sdf file in Encounter 9.1 (digital impl), where 1 field (the middle one) is left empty. Furthermore, I used the exact same .conf file and placement script, and the results are quite different. What am I missing?

    Encounter 8.1:

    (INTERCONNECT I_NCS U134/A (0.0037:0.0037:0.0037) (0.0037:0.0037:0.0037))
    (INTERCONNECT I_SCLK Q_TRANSACTIONCOMPLETE_REG/CKN (0.0045:0.0045:0.0045) (0.0045:0.0045:0.0045))

    Encounter 9.1:

    (INTERCONNECT I_NCS U134/A  (0.003::0.004) (0.003::0.004))
    (INTERCONNECT I_SCLK Q_TRANSACTIONCOMPLETE_REG/CKN  (0.000::0.000) (0.000::0.000))

     Note : we don't have OpenAccess libraries, so I export/import my layout through DEF.

     Thanks

Reply

  • Hi all, 

    I'm also working along the same lines, and have two questions regarding simulation with this kind of mixed-signal flow. Lucky for me, I have access to the gds files, so I can run DRC and LVS on my full design in virtuoso. So no problem there. However, I'm hoping to use sdf back-annotation for digital cells and full spectre analog models for the rest. I've managed to do this in another technology node with Diva and the pearl mixed-extract flow, with everything running through spectreVerilog.

    The catch is this : we don't have the DRC/LVS/Parasite extract rules for Diva or Assura.  We have to use a 3rd party tool. It works well, and I can get standard parasitic formats (SPEF, DSPF, HSPICE), seperated in hierarchical sections if I want (ie, analog-only). So I thought about importing the SPEF in Encounter (with analog blocks as black boxes), and then get my .sdf file from there. I found the box where to tell AMS about the sdf file, too.  But I'm stuck on how to pass the parasitic netlist to AMS for the analog blocks. I know that UltraSIM can attach DSPF files, but what about Spectre or APS? I've tried to look around the web, manuals and Cadence support, but nothing yet.

    My second question is about .sdf generation in Encounter. I have done it before in version 8.1, and it worked great with the spectreVerilog, AMS and another 3rd party simulator. However, the same design produces a quite different sdf file in Encounter 9.1 (digital impl), where 1 field (the middle one) is left empty. Furthermore, I used the exact same .conf file and placement script, and the results are quite different. What am I missing?

    Encounter 8.1:

    (INTERCONNECT I_NCS U134/A (0.0037:0.0037:0.0037) (0.0037:0.0037:0.0037))
    (INTERCONNECT I_SCLK Q_TRANSACTIONCOMPLETE_REG/CKN (0.0045:0.0045:0.0045) (0.0045:0.0045:0.0045))

    Encounter 9.1:

    (INTERCONNECT I_NCS U134/A  (0.003::0.004) (0.003::0.004))
    (INTERCONNECT I_SCLK Q_TRANSACTIONCOMPLETE_REG/CKN  (0.000::0.000) (0.000::0.000))

     Note : we don't have OpenAccess libraries, so I export/import my layout through DEF.

     Thanks

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