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mixed signal design flow

hon cheong

Hi ,

I would like to know about the correct flow for mixed signal design. Assuming now I have all my analog blocks readily verified in spectre, and the layout of the analog blocks pass DRC and LVS check. My digital blocks ( e.g state machine) layout are obtained from the place and route tool ( Cadence encounter). If I want to verify the system which consist of both analog and digital circuits, should I stream out the digital blocks layout into Cadence Virtuoso to combine both digital and analog layout together, then run DRC and LVS again, and extract the parasitic and rerun the whole system simulation ? But I am wondering will it take me a very long time to run the simulation as the digital blocks might consist of quite a number of gates.

 I have run AMS simulation by combining the analog blocks and VHDL code together. But I am not convinced by the simulation result as the behavioral VHDL code and the analog circuits does not seems represent the actual circuit behavior after laid out ( parasitic, fan out effect etc).

 Please advice.

Thanks in advance.

 

Regards,

hon cheong

 

Parents

  • Hi Hon Cheong,

    We have a mixed environment and we bring verilog gates into schematics and then run ams with SDF for simulation with analogue schematics

    Although we use verilog it's likely with VHDL you'll find a verilog gates netlist in the encounter directory - import this using VerilogIn in the CIW - you will need a symbol library and verilog libraries. Things you may have problems with are busses, brackets, power pins etc. You should then be able to netlist and attach sdf in the elaboration stage of AMS(NC) - you'll need to compile the sdf using ncsdf. If you have enough licenses and a new version of IC5141( not sure about IC61) then also try the APS solver which will give you 2-3x performance with full spectre accuracy. Ultrasim is also available but be careful with accuracy in things like PLL's, VCO's.

    Also we use DEF to import the design into Virtuoso rather than GDS - run defOut in encounter and Import->DEF in ICFB - you may need to clean things up by replacing abstracts and deleting blockages but shoud be OK. This way you can also LVS the whole chip

     cheers

    G

Reply

  • Hi Hon Cheong,

    We have a mixed environment and we bring verilog gates into schematics and then run ams with SDF for simulation with analogue schematics

    Although we use verilog it's likely with VHDL you'll find a verilog gates netlist in the encounter directory - import this using VerilogIn in the CIW - you will need a symbol library and verilog libraries. Things you may have problems with are busses, brackets, power pins etc. You should then be able to netlist and attach sdf in the elaboration stage of AMS(NC) - you'll need to compile the sdf using ncsdf. If you have enough licenses and a new version of IC5141( not sure about IC61) then also try the APS solver which will give you 2-3x performance with full spectre accuracy. Ultrasim is also available but be careful with accuracy in things like PLL's, VCO's.

    Also we use DEF to import the design into Virtuoso rather than GDS - run defOut in encounter and Import->DEF in ICFB - you may need to clean things up by replacing abstracts and deleting blockages but shoud be OK. This way you can also LVS the whole chip

     cheers

    G

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