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Assura LVS error

jdgriggs
attached are screen shot of a simple inverter and the layout is drc clean but debug says there is a bad net when the nets match for both...I've done this design 4 times each from scratch and generate the same errors. I have tried using th permute tool but does not seem to help LVS issue. Your assitance is appreciated Regards James
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  • bartman

    I am having an LVS problem and I noticed this post.  I am not sure if anyone is still around (based upon the 2010 responses) to reply.

    At the end of the lvs report I have the following message:

    Preprocessing layout network phase 2
    *ERROR* Device 'pfet(Generic)' on Schematic is unbound to any Layout device.
    *ERROR* Device 'nfet(Generic)' on Schematic is unbound to any Layout device.
    *ERROR* UnBound devices found.
    Info: All devices must be bound or filtered for comparison to be run.
    Exiting nvn.

    It implies that I have devices in the schematic which cannot be matched to a layout device.  I have tried this in calibre and succeeded in getting a clean LVS; so I know the layout and schematic do match.  I would like to have assura working as well.  One possible issue is in the use of multiplicity; m>1 for every transistor in the schematic.   The LVS checks using assura for devices which have m=1 have worked.  Is it possible to fix this problem ?

    alan

Reply
  • bartman

    I am having an LVS problem and I noticed this post.  I am not sure if anyone is still around (based upon the 2010 responses) to reply.

    At the end of the lvs report I have the following message:

    Preprocessing layout network phase 2
    *ERROR* Device 'pfet(Generic)' on Schematic is unbound to any Layout device.
    *ERROR* Device 'nfet(Generic)' on Schematic is unbound to any Layout device.
    *ERROR* UnBound devices found.
    Info: All devices must be bound or filtered for comparison to be run.
    Exiting nvn.

    It implies that I have devices in the schematic which cannot be matched to a layout device.  I have tried this in calibre and succeeded in getting a clean LVS; so I know the layout and schematic do match.  I would like to have assura working as well.  One possible issue is in the use of multiplicity; m>1 for every transistor in the schematic.   The LVS checks using assura for devices which have m=1 have worked.  Is it possible to fix this problem ?

    alan

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