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Assura LVS error

jdgriggs
attached are screen shot of a simple inverter and the layout is drc clean but debug says there is a bad net when the nets match for both...I've done this design 4 times each from scratch and generate the same errors. I have tried using th permute tool but does not seem to help LVS issue. Your assitance is appreciated Regards James
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  • bartman

    Hi Quek,


    I created a new post this morning.  But, I am not sure if I did it correctly.  I am checking it now.

    best regards,

    alan

Reply
  • bartman

    Hi Quek,


    I created a new post this morning.  But, I am not sure if I did it correctly.  I am checking it now.

    best regards,

    alan

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