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Open Instance connections Assura LVS error

jdgriggs
Simple inverter as a Ring Oscillator Design is DRC clean but the Assura LVS brings up Nets Mismatch Tool...Open Instance Connections...

I've tried severval ways to remove error but to no avail.  Any insight will be appreciated.

attach are the screen shot

  • Here is the lvs file 

     

     

    *******************************************************************************

    ****** 5_ring_oscillator_1 schematic Ring_Oscillator_inv_sch_1 <vs> 5_ring_oscillator_1 layout Ring_Oscillator_inv_sch_1

    *******************************************************************************

     

    Pre-expand Statistics

    ====================== Original

    Cell/Device schematic layout

    (inverter schematic Ring_Oscillat...) Cell 5 5

    (buffer schematic Ring_Oscillator...) Cell 1 1

    (bufferx2 schematic Ring_Oscillat...) Cell 1 1

    (mosvar) Generic 1 1

    ------ ------

    Total 8 8

    Filter Statistics

    ================= Original Filtered

    Cell/Device schematic layout schematic layout

    (buffer) Cell 1 1 1 1

    (bufferx2) Cell 1 1 1 1

    (inverter) Cell 5 5 5 5

    (mosvar) Generic 0 0 0 0

    (mosvar_m0) Generic 1 1 1 1

    Reduce Statistics

    ================= Filtered Reduced

    Cell/Device schematic layout schematic layout

    (buffer) Cell 1 1 1 1

    (bufferx2) Cell 1 1 1 1

    (inverter) Cell 5 5 5 5

    (mosvar) Generic 0 0 0 0

    (mosvar_m0) Generic 1 1 1 1

    Match Statistics

    ================ Total Unmatched

    Cell/Device schematic layout schematic layout

    (buffer) Cell 1 1 0 0

    (bufferx2) Cell 1 1 0 0

    (inverter) Cell 5 5 0 0

    (mosvar) Generic 0 0 0 0

    (mosvar_m0) Generic 1 1 0 0

    ------ ------ ------ ------

    Total 8 8 0 0

    Match Statistics for Nets 12 12 0 0

    ==========================================================[5_ring_oscillator_1]

    ====== Open Instance Connections ==============================================

    ===============================================================================

    Layout net: |I25/vdd should connect to:

    L |I25/avC7

    Layout net: |I23/vdd should connect to:

    L |I23/avC7

    　

    ==========================================================[5_ring_oscillator_1]

    ====== Summary of Errors ======================================================

    ===============================================================================

    Schematic Layout Error Type

    --------- ------ ----------

    - 2 Open Instance Connections

    　

  • Hi jdgriggs

    I think perhaps the lvs mismatch can be resolved by joining up the vdd rails of the 2 instances. : )

    Best regards
    Quek

  • Hey Quek thanks for the reply..the rails are suppose to be separated it's the buffer stage that is causing the error... as indicated in by lvs error file.

     JG

  • Hi JG

    That's right! Sorry that I had not looked at your schematic carefully. : P

    Would you please upload the following 2 ascii files and also the cls file?

    terminal>vldbToCdl design.lnn > design.lnn.ascii
    terminal>vldbToCdl design.snn > design.snn.ascii

    Please upload the files, not cut and paste.

    Thanks
    Quek

  • let's try this one more time..Quek here are the files you requested
     
    thanks
    JG

  • Hi JG

    Thanks for the files. It appears that your nwells in buffer and buffer2 cells are not connected to the vdd rails. I thought that there might be something wrong with geomConnect section in extract.rul file but since the nwell of the inverters got the vdd connection, it seems to mean that Assura can see M1->cont->Nwell connectivity. This is indeed quite puzzling.

    Would you please upload a snapshot of the layout with only nwell, poly and cont layers?

    Thanks
    Quek

  • Hi Quek

    Here is the picture you requested also I included my LVS run files for the oscillator.  It really is a mystery for me as well bcause I have done this design 5 times already and I come to the same impass.

    Thanks for whatever insight you can provide.

    Regards

    JG

     

     

    Hi JG

    Thanks for the files. It appears that your nwells in buffer and buffer2 cells are not connected to the vdd rails. I thought that there might be something wrong with geomConnect section in extract.rul file but since the nwell of the inverters got the vdd connection, it seems to mean that Assura can see M1->cont->Nwell connectivity. This is indeed quite puzzling.

    Would you please upload a snapshot of the layout with only nwell, poly and cont layers?

    Thanks
    Quek

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