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LVS on mixed signal circuits

hon cheong

Hi,

If I would like to run LVS on a circuit that compose of both analog circuits (handcrafted) as well as digital circuits ( layout generated by Encounter), how can I do that ? while I have schematic for my analog circuits, I do not have schematic for my digital circuits ( I have VHDL code, structural verilog files generated by design compiler, as well as layout generated by Encounter).

Please advice.

Thank You.
Regards,
Hon Cheong

Parents
  • Tongju

    Hi, Hon Cheong,

    I don't think you need to get your cdl file that describe your stdcell circuits into FE. FE only need LEF, .lib, and .cdb files for stdcells. However, you need to integrate all of those netlist files (stdcell, cdl, final gate netlist from FE, and your analog circuits) together to run your fullchip, tapeout LVS check.

    I thought that one way is to create the stdcell library in the dfII by using the gds and cdl files (I don't know whether it is possible or how to do it). Then, import FE netlist into dfII, then, you could do your TO LVS check inside dfII.

     The other way is to stitch those files together by LVS check tools. But I don't know the detailed steps. Someone in this forum may have better idea.

     Tongju

Reply
  • Tongju

    Hi, Hon Cheong,

    I don't think you need to get your cdl file that describe your stdcell circuits into FE. FE only need LEF, .lib, and .cdb files for stdcells. However, you need to integrate all of those netlist files (stdcell, cdl, final gate netlist from FE, and your analog circuits) together to run your fullchip, tapeout LVS check.

    I thought that one way is to create the stdcell library in the dfII by using the gds and cdl files (I don't know whether it is possible or how to do it). Then, import FE netlist into dfII, then, you could do your TO LVS check inside dfII.

     The other way is to stitch those files together by LVS check tools. But I don't know the detailed steps. Someone in this forum may have better idea.

     Tongju

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