LVS on mixed signal circuits

Hi, Hon Cheong,

You need to get the final, gate level verilog netlist from the final database of FE (you could do it by GUI, or by tcl command "saveNetlist fileName"). This netlist could be imported into dfII (File->Import->Verilog) to create schematic views for the circuit and then, you could use your normal LVS flow to check it  together with your analog circuit.

Tongju 

Hi Tongju,

Thanks for your reply, it give me more insight into the LVS flow. However, since I am provided with the standard cell netlist by ARM, do I need to include the standard cell netlist (ibmrfvt.cdl)  while saving my netlist in SOC Encounter ?

Thanks.

Hon Cheong

Hi, Hon Cheong,

I don't think you need to get your cdl file that describe your stdcell circuits into FE. FE only need LEF, .lib, and .cdb files for stdcells. However, you need to integrate all of those netlist files (stdcell, cdl, final gate netlist from FE, and your analog circuits) together to run your fullchip, tapeout LVS check.

I thought that one way is to create the stdcell library in the dfII by using the gds and cdl files (I don't know whether it is possible or how to do it). Then, import FE netlist into dfII, then, you could do your TO LVS check inside dfII.

 The other way is to stitch those files together by LVS check tools. But I don't know the detailed steps. Someone in this forum may have better idea.

 Tongju

 Hon,

I'm going to move this thread to the Custom IC forum. I think you'll get more help with this particular issue there.

- Kari

Hi,

 I think we can do LVS for mixed signal circuit by first convert verilog code to spice netlist, then create a schematic view from the spice netlist. Then we can do LVS just like what we did for analog circuit. I have found the solution in this link:

http://circuitdesignworld.wordpress.com/2010/11/11/how-to-run-lvs-for-mixed-signal-circuit/

 hon cheong

Hi Hon Cheong

If you are using Assura, there is no need to manually convert your structural verilog codes to spice format. Assura can read in the verilog files and does conversion automatically. The relevant standard cell cdl files for the verilog files have to be included too.

If you would like to first convert your verilog codes to cdl format, you can use Assura's "netReader" tool to do it. Please refer to COS solution 11288720 for more details.

PVS is also able to read in verilog directly. The equivalent of "netReader" for PVS is "v2cdl" tool.

Best regards
Quek

Hi Quek,

 Thanks for your reply. I am using Calibre. Although I can do LVS for digital circuit comparing verilog codes and layout, I wonder how is it possible to do it for mixed signal circuits. I need to interconnect my digital circuit with analog blocks. Therefore I take the simplest approach by converting all of them into schmeatic view.

 Best Regards,

Hon Cheong

Hi Hon Cheong

Currently it looks like you are doing mixed signal lvs as follows:
a. Import all cdl files as schematic
b. Import all verilog files as schematic
c. Do lvs on imported schematics and layout

You can also do it as follows without importing cdl and verilog:
a. Use v2lvs to convert verilog netlist to cdl format
b. Compare with layout using toplevel cdl netlist and the converted cdl files

Best regards
Quek