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LVS on mixed signal circuits

hon cheong

Hi,

If I would like to run LVS on a circuit that compose of both analog circuits (handcrafted) as well as digital circuits ( layout generated by Encounter), how can I do that ? while I have schematic for my analog circuits, I do not have schematic for my digital circuits ( I have VHDL code, structural verilog files generated by design compiler, as well as layout generated by Encounter).

Please advice.

Thank You.
Regards,
Hon Cheong

Parents

  • Hi Hon Cheong

    If you are using Assura, there is no need to manually convert your structural verilog codes to spice format. Assura can read in the verilog files and does conversion automatically. The relevant standard cell cdl files for the verilog files have to be included too.

    If you would like to first convert your verilog codes to cdl format, you can use Assura's "netReader" tool to do it. Please refer to COS solution 11288720 for more details.

    PVS is also able to read in verilog directly. The equivalent of "netReader" for PVS is "v2cdl" tool.

    Best regards
    Quek

Reply

  • Hi Hon Cheong

    If you are using Assura, there is no need to manually convert your structural verilog codes to spice format. Assura can read in the verilog files and does conversion automatically. The relevant standard cell cdl files for the verilog files have to be included too.

    If you would like to first convert your verilog codes to cdl format, you can use Assura's "netReader" tool to do it. Please refer to COS solution 11288720 for more details.

    PVS is also able to read in verilog directly. The equivalent of "netReader" for PVS is "v2cdl" tool.

    Best regards
    Quek

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