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PSS simulation

svilen

 Hi,

 

I'm trying to run pss and pnoise simulations on a switched capacitor circuit. The only periodic voltage source in the circuit is a clock but the problem is that switching and sampling doesn't happen on the clock. It clocks a logic that produces waveforms which control sampling and switching in the circuit. When I run the pss, although I specify the beat frequency to be the frequency of the actual sampling signal it seems that the simulator still detects the clock stimuli (which is pwlf source) and I have the feeling it periodizes the analysis with repect to the clock, not to the actual sampling waveform.

Is there anyway to trick the simulator not to take the clock but the logic signal that acrually does the sampling? I can not remove the logic block that's being clocked or substitute the sampling signal with a voltage source.

Thanks

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  • Andrew Beckett

    Your post is a bit confusing. Isn't the clock what is doing the sampling? (or at least some signal derived from the clock?).

    A few things that might help clarify what is going on and help you to understand what to set up:

    1. If you have a pwl source that you want to be enabled during the shooting interval itself, then it must be periodic. For this the pwlperiod parameter (and maybe the pwlperiodstart parameter too) needs to be set. Otherwise the analysis will run through to the end of the pwl source as part of the initial transient, and then that signal will be steady for the rest of the analysis (essentially this happens for any non-periodic source - you obviously can't do a periodic analysis over a non-periodic source).
    2. When performing a pnoise analysis, you wouldn't normally have a large signal "signal" input to the circuit (i.e. the main input signal). In this case it would just be the clock. The large signal input would only be needed if you wanted to investigate the intermodulation of the noise with the large signal input (usually when the input signal is big enough to cause appreciable distortion).
    3. Your "beat" frequency must be the greatest common divider (or lower, of course) of all the input signals. If the logic circuitry contains a divider, then it will need to include the divided down frequency as part of that calculation. If there's no divider, usually letting ADE to compute this is sufficient (if you've specified pwlperiod it would be able to do that even with a PWL source).
    4. Looking at the time domain waveforms (Turn on the saving of the initial waveforms, and compare this with the time domain waveforms during the shooting inteval) should help you debug what is going on.

    Otherwise you'll need to give more details - for example, the parts of the input.scs which define the sources, and the analysis statements at the bottom. That may allow us to figure out what is going wrong.

    Best Regards,

    Andrew.

Reply
  • Andrew Beckett

    Your post is a bit confusing. Isn't the clock what is doing the sampling? (or at least some signal derived from the clock?).

    A few things that might help clarify what is going on and help you to understand what to set up:

    1. If you have a pwl source that you want to be enabled during the shooting interval itself, then it must be periodic. For this the pwlperiod parameter (and maybe the pwlperiodstart parameter too) needs to be set. Otherwise the analysis will run through to the end of the pwl source as part of the initial transient, and then that signal will be steady for the rest of the analysis (essentially this happens for any non-periodic source - you obviously can't do a periodic analysis over a non-periodic source).
    2. When performing a pnoise analysis, you wouldn't normally have a large signal "signal" input to the circuit (i.e. the main input signal). In this case it would just be the clock. The large signal input would only be needed if you wanted to investigate the intermodulation of the noise with the large signal input (usually when the input signal is big enough to cause appreciable distortion).
    3. Your "beat" frequency must be the greatest common divider (or lower, of course) of all the input signals. If the logic circuitry contains a divider, then it will need to include the divided down frequency as part of that calculation. If there's no divider, usually letting ADE to compute this is sufficient (if you've specified pwlperiod it would be able to do that even with a PWL source).
    4. Looking at the time domain waveforms (Turn on the saving of the initial waveforms, and compare this with the time domain waveforms during the shooting inteval) should help you debug what is going on.

    Otherwise you'll need to give more details - for example, the parts of the input.scs which define the sources, and the analysis statements at the bottom. That may allow us to figure out what is going wrong.

    Best Regards,

    Andrew.

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