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PSS simulation

svilen
svilen over 14 years ago

 Hi,

 

I'm trying to run pss and pnoise simulations on a switched capacitor circuit. The only periodic voltage source in the circuit is a clock but the problem is that switching and sampling doesn't happen on the clock. It clocks a logic that produces waveforms which control sampling and switching in the circuit. When I run the pss, although I specify the beat frequency to be the frequency of the actual sampling signal it seems that the simulator still detects the clock stimuli (which is pwlf source) and I have the feeling it periodizes the analysis with repect to the clock, not to the actual sampling waveform.

Is there anyway to trick the simulator not to take the clock but the logic signal that acrually does the sampling? I can not remove the logic block that's being clocked or substitute the sampling signal with a voltage source.

Thanks

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  • Andrew Beckett
    Andrew Beckett over 14 years ago

    Your post is a bit confusing. Isn't the clock what is doing the sampling? (or at least some signal derived from the clock?).

    A few things that might help clarify what is going on and help you to understand what to set up:

    1. If you have a pwl source that you want to be enabled during the shooting interval itself, then it must be periodic. For this the pwlperiod parameter (and maybe the pwlperiodstart parameter too) needs to be set. Otherwise the analysis will run through to the end of the pwl source as part of the initial transient, and then that signal will be steady for the rest of the analysis (essentially this happens for any non-periodic source - you obviously can't do a periodic analysis over a non-periodic source).
    2. When performing a pnoise analysis, you wouldn't normally have a large signal "signal" input to the circuit (i.e. the main input signal). In this case it would just be the clock. The large signal input would only be needed if you wanted to investigate the intermodulation of the noise with the large signal input (usually when the input signal is big enough to cause appreciable distortion).
    3. Your "beat" frequency must be the greatest common divider (or lower, of course) of all the input signals. If the logic circuitry contains a divider, then it will need to include the divided down frequency as part of that calculation. If there's no divider, usually letting ADE to compute this is sufficient (if you've specified pwlperiod it would be able to do that even with a PWL source).
    4. Looking at the time domain waveforms (Turn on the saving of the initial waveforms, and compare this with the time domain waveforms during the shooting inteval) should help you debug what is going on.

    Otherwise you'll need to give more details - for example, the parts of the input.scs which define the sources, and the analysis statements at the bottom. That may allow us to figure out what is going wrong.

    Best Regards,

    Andrew.

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  • svilen
    svilen over 14 years ago

     Hi Andrew,

    Thanks for your reply.  The clock is not doing the sampling. Clock is 1.2GHz and clocks a logic which based on it and on an asynchronous input  generates a signal, periodic in its nature, which then clocks the switches in the SC core.So, in short, the sampling signal is periodic and "kind of" synchronized to the clock but only kind of because of the asynchronous signal. The sampling signal is 27.918MHz while the clock is 1.2GHz.

    It is a bit unclear what you wrote in 1). Where do I find  pwlperiod and pwlperiodstart  ? 

    A side question: which document in the cadence documentation describes the settings and GUI for pss, pac and pnoise? What I have read is just Ken Kundert's paper on simulating SC circuits.

    My 1.2GHz voltage source is defines as pwlf source and basically is a clock with a period of 833ps and starts from 0 and ends at about 198ns.

    The analysis statements are :

    simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=65.0 \
        tnom=27 scalem=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 digits=5 \
        cols=80 pivrel=1e-3 sensfile="../psf/sens.output" checklimitdest=psf
    pss  pss  fund=27.918e6  harms=0  errpreset=moderate  tstab=72.2194n
    +    \
        swapfile="/lsi/dv/analogsim/svilen/spyder/test_Pnoise/spectre/schematic/distributed/Pnoise/swap"
    +    maxacfreq=2.8e9  annotate=status
    pnoise  (  dac_diff  gnda  )  pnoise  start=10  stop=13.959e6
    +       dec=100  maxsideband=100  noisetype=timedomain  numberofpoints=0
    +       noisetimepoints=[35n]  annotate=status

     

     

    The PSS starts like this:

    =================================
    `pss': time = (0 s -> 219.661 ns)
    =================================
    Important parameter values in tstab integration:
        start = 0 s
        outputstart = 0 s
        stop = 219.661 ns
        period = 35.8192 ns
        step = 219.661 ps
        maxstep = 1.43277 ns
        ic = all
        skipdc = no
        reltol = 1e-03
        abstol(V) = 1 uV
        abstol(I) = 1 pA
        temp = 65 C
        tnom = 27 C
        tempeffects = all
        method = traponly
        lteratio = 0
        relref = sigglobal
        cmin = 0 F
        gmin = 1 pS

     

    And the PNOISE analysis starts like:


    **************************************************************
    Periodic Noise Analysis `pnoise': freq = (10 Hz -> 13.959 MHz)
    **************************************************************
    Using the operating-point information generated by PSS analysis `pss'.
    Working on time-domain noise timepoint 1 of 1 (time=218.841 ns).

     

    Why is it working on timepoint 218.841ns when I have asked it to calculate the noise at 35ns?

     

    Thanks again

     

     

     

     

     

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  • Andrew Beckett
    Andrew Beckett over 14 years ago

    OK, I've set something simple up to show the problem you're seeing - in order to illustrate it. I have this as a netlist:

    //
    parameters fsamp=27.918M
    
    vpwl (pwl 0) vsource type=pwl file="clock.pwl"
    vsample (sample 0) vsource type=pulse period=1/fsamp width=0.5/fsamp 
    + rise=1n fall=1n val0=0 val1=1
    
    rsamp (sample sampout) resistor r=100
    csamp (sampout 0) capacitor c=0.1p
    
    pss pss fund=fsamp tstab=72.2914n
    
    pnoise (sampout 0) pnoise start=10 stop=100 dec=5 maxsideband=10 
    + noisetype=timedomain numberofpoints=0 noisetimepoints=[35n] annotate=status
    

    And then this as my clock.pwl file:

    0 0
    10n 2
    20n 2
    30n 0
    106n 0
    107n 2
    108n 2
    109n 0
    111.55n 0
    

    In order to get the numbers you're seeing, the last point in the pwl file must be at 111.55n not 198n.

    Don't worry at this stage that the clock.pwl file is not representing your 1.2GHz clock (I was just being lazy when creating this file; it's suffiicient to explain what is going on). The first part of the PSS simulation will start at time 0, and then go to the point at which all the sources become periodic (111.55n, because the pwl source is not seen as periodic), and then simulate any tstab time you've set (72.2914n) and also 1 period of the PSS fundamental (1/27.918M = 35.819n). So that's a total of 219.661ns (which is what you see). Each PSS iteration will then re-simulate the last 35.819n of this over and over again (i.e. from 183.841 ns -> 219.661 ns).

    The timedomain noise sample you have asked for is at 35ns through this 35.819ns period, so therefore will be 0.819ns from the end of the 219.661n section (i.e. 218.841ns).

    So the real problem is that your pwl file is not being treated as periodic - understandably, because the simulator had no idea it was meant to be periodic and not a one-off reset pulse (say).

    In order to make it periodic, you need to specify the pwlperiod parameter (which on the analogLib vpwlf source shows up as  "Period of the PWL", or on the analogLib vsource component in pwl mode shows up as "Period" (there's also "Period Start Time" which corresponds to the pwlperiodstart parameter I mentioned earlier).

    Having made this periodic (I suggest running a long transient just with this pwl source just to make sure it's repeating OK), the problem is that your PSS fundamental will need be commensurate with both the 27.918MHz sampling signal and your 1.2GHz clock. Unfortunately the greatest common divisor of both those frequencies is 6kHz (think about it - to do a Fourier analysis, you're going to need whole numbers of both frequencies). Since that corresponds to 200000 cycles of the clock signal, your simulation would be very slow, and will need an enormous amount of memory.

    There are several choices:

    1. Adjust your frequencies a little to make them commensurate (or more commensurate). For example, a Fsample of 28MHz would mean a common frequency of 4MHz. That's still 300 cycles of the clock, but may be manageable.
    2. Check to see if the clock (or the sampling signal) really needs to be there to check out the noise performance. Dealing with a single frequency makes the simulation much simpler
    3. You could potentially use QPSS (Quasi-periodic steady state) with the two frequencies, but the trouble is that two highly non-linear signals is very expensive to simulate. QPSS (shooting) is intended primarily for when you have one strongly non-linear, and the rest weakly non-linear signals. With Harmonic Balance, all signals are typically weakly non-linear, but you could ask for lots of harmonics of one of them; asking for lots of harmonics for multiple signals is likely to lead to very slow and memory hungry simulation time though.

    Unfortunately it's hard for me to be precise because I don't quite know what the logic you're describing is doing, and would probably need to see it. It might be easier to talk to Cadence Customer Support so that we can see more of the data and give you more focused advice?

    Best Regards,

    Andrew.

     

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  • svilen
    svilen over 14 years ago

     Thanks a lot for the valuable information. In addition to your suggested solutions, your explanation promted to me 1 or 2 more ways I can try and solve the problem.

    One more question. When I'm runnig PSS I frequently get  an error and the simulation exits because of not enough memory although I define a swap file. Isn't the swap file availability suppose to mitigate this problem? What apart from maxacfreq contributes to the memory usage when doing pss?

    Thanks

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  • Tawna
    Tawna over 14 years ago

    Hi Svilen,

     

    I just happened to see your post....  You may want to try 64 bit spectre (if you aren't using it already).

    Another thing is to look at:  (type this into an xterm)

    spectre -h rfmemory  

     

    best regards,

    Tawna 

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  • svilen
    svilen over 14 years ago

     Hi,

    Thanks for the replies. I finally got the pss working. At least so it seems. Next is to see if pnoise results make sense.

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  • JackieTheBanan
    JackieTheBanan over 6 years ago in reply to svilen

    How to set the stop time of PSS simulation sir? I am a foolish student as can easily be obtained from my user alias. : )

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  • JackieTheBanan
    JackieTheBanan over 6 years ago in reply to Andrew Beckett

    Excuse me Mr.Beckett, I and my friends are running a Virtuoso 6.1.5 and are wondering how to set the stop time in PSS simulation properly, could you please tell me? I will be really appreciated that! : )

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  • Andrew Beckett
    Andrew Beckett over 6 years ago in reply to JackieTheBanan
    JackieTheBanan said:
    I am a foolish student as can easily be obtained from my user alias. : )

    This is the best post I've seen on the forums - it made me laugh out loud (much to the amusement of my colleagues)!

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  • Andrew Beckett
    Andrew Beckett over 6 years ago in reply to JackieTheBanan

    I don't really know what you mean by stop time. There is no stop time in PSS...

    Perhaps you should post a new question (the forum guidelines ask you not to post in old threads anyway) with details of what you're trying to do and then I or somebody else can give a more focused answer?

    Regards,

    Andrew.

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