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Import Verilog

eppramod
Hi, Don't know if this query was raised before here. I am new to doing "Import ==> Verilog" in Cadence Virtuoso. I am having a gate level Verilog netlist and was trying to do Import==> Verilog function through Cadence Virtuoso(icfb). I am getting the import to work but unfortunately the reference dfII library which i am using for "component" symbols have VDD and VSS pins in their symbols. After import I am seeing that these ports are unconnected in the schematic view(as there are no VDD/VSS definition in the verilog netlist). Is there a way to have these pins connected after import? Thanks in advance.
Parents

  • Hello Quek,

     

    We are having the same issue that eppramod has brought up with the VDD and VSS netlist. Most PDK's from fabs have digital cell libraries without VDD and VSS (they usually have  VDD! and VSS! and SUB!) and we are having to edit these cell libraries to create VDD, VSS and SUB - we need this to use standard digital cells in handdrawn mixed signal schematics anyway. So we are having to copy over the standard cell library and then hand edit the standard cell library to make it free of the global nets (VDD!, VSS! and SUB!). But after this, if we used such a library to import verilog gate level netlists into cadence we dont have connectivity for the VDD, VSS and SUB pins. Can you help with the following

     1) A Skill script to change a standard cell library and convert standard cells such that VDD! can be changed to VDD,  VSS! -> VSS and SUB! -> SUB.

    2) You mentioned a Skill script that can add wires to VDD, VSS and SUB after a verilog file has been imported - can you please provide this? Also does this work heirarchically?

     Please help. Thanks.

Reply

  • Hello Quek,

     

    We are having the same issue that eppramod has brought up with the VDD and VSS netlist. Most PDK's from fabs have digital cell libraries without VDD and VSS (they usually have  VDD! and VSS! and SUB!) and we are having to edit these cell libraries to create VDD, VSS and SUB - we need this to use standard digital cells in handdrawn mixed signal schematics anyway. So we are having to copy over the standard cell library and then hand edit the standard cell library to make it free of the global nets (VDD!, VSS! and SUB!). But after this, if we used such a library to import verilog gate level netlists into cadence we dont have connectivity for the VDD, VSS and SUB pins. Can you help with the following

     1) A Skill script to change a standard cell library and convert standard cells such that VDD! can be changed to VDD,  VSS! -> VSS and SUB! -> SUB.

    2) You mentioned a Skill script that can add wires to VDD, VSS and SUB after a verilog file has been imported - can you please provide this? Also does this work heirarchically?

     Please help. Thanks.

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