Import Verilog

Hi eppramod

There is currently no easy way to resolve this. We can solve the problem using either of the following methods:
a. Use a perlscript to add in VDD and VSS connections to the verilog netlist
b. Use a skillscript to route the VDD and VSS connections after importing the netlist

You can use the following perlscript. It adds VDD and VSS to the verilog netlist. It is also available in COS solution 11598626.

Best regards
Quek


#!/usr/bin/perl

# This script adds power pins to a verilog netlist
# Usage: addpower.pl input.v output.v

if(@ARGV<2) {
   die("Please enter 2 inputs: E.g. addpower.pl input.v output.v\n")
} #if

if(!open(inPort, @ARGV[0])) {
   die("Cannot open file @ARGV[0]\n")
} #if

if(!open(outPort, ">@ARGV[1]")) {
   die("Cannot create file @ARGV[1]\n")
} #if

$pin1="VDD";
$pin2="VSS";

while( chomp($inLine=<inPort>) ) {
   $inLine2 = $inLine;
   $inLine2 =~ s/^ *//;
   @myList=split / /, $inLine2;
   if( @myList[0] =~ /module/ ) {
      $inLine=~s/\(/\($pin1, $pin2, /;
   } #if
   if( @myList[0] =~ /input/ ) {
      $inLine=~s/input/inout $pin1, $pin2;\n  input/;
   } #if
   if( $inLine =~ /.*\(..*\(.*\).*/ ) {
      $inLine=~s/\(/\(.$pin1\($pin1\), .$pin2\($pin2\), /;
   } #if
   print outPort $inLine, "\n";
} #while

Hello Quek,

We are having the same issue that eppramod has brought up with the VDD and VSS netlist. Most PDK's from fabs have digital cell libraries without VDD and VSS (they usually have  VDD! and VSS! and SUB!) and we are having to edit these cell libraries to create VDD, VSS and SUB - we need this to use standard digital cells in handdrawn mixed signal schematics anyway. So we are having to copy over the standard cell library and then hand edit the standard cell library to make it free of the global nets (VDD!, VSS! and SUB!). But after this, if we used such a library to import verilog gate level netlists into cadence we dont have connectivity for the VDD, VSS and SUB pins. Can you help with the following

 1) A Skill script to change a standard cell library and convert standard cells such that VDD! can be changed to VDD,  VSS! -> VSS and SUB! -> SUB.

2) You mentioned a Skill script that can add wires to VDD, VSS and SUB after a verilog file has been imported - can you please provide this? Also does this work heirarchically?

 Please help. Thanks.

Hi Ntrichy

Just a gentle reminder not to append to an old thread. This thread has already ended in Jan 2011. Please always start your question in a new thread.

1. You can modify the skillscript in COS article 1843566.

2. I think there is a mis-understanding. I meant that it is possible to code a skillscript to add VDD and VSS wire stubs to the required pins. I don't have such a script.

Best regards
Quek

Hi Quek,

you can help on this,  after routing we can change the component for same net, but component size is too big, that case routing as unconnected the component how to auto connect the these validate component.

Hi madhesh

Would you please kindly start a new thread for your issue? Appending to an old thread is a violation of forum rules. You might also want to consider breaking down your question in point form so that we can understand the issue more issues. Thanks


Best regards
Quek