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Import Verilog

eppramod
Hi, Don't know if this query was raised before here. I am new to doing "Import ==> Verilog" in Cadence Virtuoso. I am having a gate level Verilog netlist and was trying to do Import==> Verilog function through Cadence Virtuoso(icfb). I am getting the import to work but unfortunately the reference dfII library which i am using for "component" symbols have VDD and VSS pins in their symbols. After import I am seeing that these ports are unconnected in the schematic view(as there are no VDD/VSS definition in the verilog netlist). Is there a way to have these pins connected after import? Thanks in advance.
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  • Hi Ntrichy

    Just a gentle reminder not to append to an old thread. This thread has already ended in Jan 2011. Please always start your question in a new thread.

    1. You can modify the skillscript in COS article 1843566.

    2. I think there is a mis-understanding. I meant that it is possible to code a skillscript to add VDD and VSS wire stubs to the required pins. I don't have such a script.

    Best regards
    Quek

Reply

  • Hi Ntrichy

    Just a gentle reminder not to append to an old thread. This thread has already ended in Jan 2011. Please always start your question in a new thread.

    1. You can modify the skillscript in COS article 1843566.

    2. I think there is a mis-understanding. I meant that it is possible to code a skillscript to add VDD and VSS wire stubs to the required pins. I don't have such a script.

    Best regards
    Quek

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