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Mark Net Configuration

TjaartOpperman
I'm getting some problems when using mark nets in VLE on IC614. When I highlight a net, all the layers in the layout gets highligted like there is some kind of short. It seems like the tool uses the layers defined under viaDefs( standardViaDefs (.. )) in the techfile to establish connectivity. I believe that the short is caused by a via definition that is used to connect the ACTIVE layer to the METAL1 layer. The ACTIVE layer is drawn over the gate of a MOS, causing the tool to interpret it as a short, when its actually electrically unconnected. So I've seen that its is possible to select Via Layers manually when using the Mark Net tool. I find this solution a bit tedious however, and I want to know if there are any alternatives?
Parents

  • Mark Net in IC614 supports the idea of "Stop Layers" (you can specify that ACTIVE is stopped by POLY, so it will not follow connection under the gate of a transistor).

    This can be set up so that it is initialized automatically by creating a file called "stopLayers" in the appropriate place. Search in cdnshelp for stopLayers and it will explain how to do this.

    Regards,

    Andrew.

Reply

  • Mark Net in IC614 supports the idea of "Stop Layers" (you can specify that ACTIVE is stopped by POLY, so it will not follow connection under the gate of a transistor).

    This can be set up so that it is initialized automatically by creating a file called "stopLayers" in the appropriate place. Search in cdnshelp for stopLayers and it will explain how to do this.

    Regards,

    Andrew.

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