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Mark Net Configuration

TjaartOpperman
I'm getting some problems when using mark nets in VLE on IC614. When I highlight a net, all the layers in the layout gets highligted like there is some kind of short. It seems like the tool uses the layers defined under viaDefs( standardViaDefs (.. )) in the techfile to establish connectivity. I believe that the short is caused by a via definition that is used to connect the ACTIVE layer to the METAL1 layer. The ACTIVE layer is drawn over the gate of a MOS, causing the tool to interpret it as a short, when its actually electrically unconnected. So I've seen that its is possible to select Via Layers manually when using the Mark Net tool. I find this solution a bit tedious however, and I want to know if there are any alternatives?
Parents

  •  Hi,

    I think my question is related to the current subject;

    How can I "Select Via Layers for Mark Net" with different purposes ?

    The problem is that if I select for example "poly" as one layer ... it will propagate through list("poly" "drawing"), list("poly" "pin"), etc .. all possible "poly" cases, and I want only one of them.

     

    Best Regards,

    Adrian

Reply

  •  Hi,

    I think my question is related to the current subject;

    How can I "Select Via Layers for Mark Net" with different purposes ?

    The problem is that if I select for example "poly" as one layer ... it will propagate through list("poly" "drawing"), list("poly" "pin"), etc .. all possible "poly" cases, and I want only one of them.

     

    Best Regards,

    Adrian

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