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JK Flip Flop

Anand T

Hello Everyone,

 I am new to cadence and hav designed a JK FlipFlop.

I need to give a clock signal so that the inputs trigger only at the rising edge.

Now the outputs change for a change in input if the clock signal is high.

Its acting like an Edge triggered flipflop.

I want to know how to make the clock edge triggered.

I am implementing it in cadence virtuoso...Pls do help me out with this.

 

Thanks in advance.

Parents

  • Hi Anand,

    I do not think you have given sufficient details for anyone to be able to answer your question. You say you are using Virtuoso, but you do not say which tool or flow you have used: is your JKFF a transistor based schematic design? a layout, a verilog module, Verilog-A (or Verilog-AMS) or something else (e.g. using an external subcircuit/macromodel for a block)?  Which version of the tools are you using? If simulating the design, are you using Spectre, and if so, which version? Or perhaps you are using a digital simulator, e.g. NC-Verilog ?

    An imprecise question will yield an imprecise answer, or no answer at all.  I cannot glean enough information from your question to know how to answer it, sorry.

    Regards,

    Lawrence.

Reply

  • Hi Anand,

    I do not think you have given sufficient details for anyone to be able to answer your question. You say you are using Virtuoso, but you do not say which tool or flow you have used: is your JKFF a transistor based schematic design? a layout, a verilog module, Verilog-A (or Verilog-AMS) or something else (e.g. using an external subcircuit/macromodel for a block)?  Which version of the tools are you using? If simulating the design, are you using Spectre, and if so, which version? Or perhaps you are using a digital simulator, e.g. NC-Verilog ?

    An imprecise question will yield an imprecise answer, or no answer at all.  I cannot glean enough information from your question to know how to answer it, sorry.

    Regards,

    Lawrence.

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