I am new to cadence and hav designed a JK FlipFlop.
I need to give a clock signal so that the inputs trigger only at the rising edge.
Now the outputs change for a change in input if the clock signal is high.
Its acting like an Edge triggered flipflop.
I want to know how to make the clock edge triggered.
I am implementing it in cadence virtuoso...Pls do help me out with this.
Thanks in advance.
I do not think you have given sufficient details for anyone to be able to answer your question. You say you are using Virtuoso, but you do not say which tool or flow you have used: is your JKFF a transistor based schematic design? a layout, a verilog module, Verilog-A (or Verilog-AMS) or something else (e.g. using an external subcircuit/macromodel for a block)? Which version of the tools are you using? If simulating the design, are you using Spectre, and if so, which version? Or perhaps you are using a digital simulator, e.g. NC-Verilog ?
An imprecise question will yield an imprecise answer, or no answer at all. I cannot glean enough information from your question to know how to answer it, sorry.
Presumably you haven't actually designed a JK Flip Flop then. Countless references on google for this, including http://en.wikipedia.org/wiki/JK_flip_flop
I don't think this is anything to do with implementing the flip flop in Virtuoso - but more about ensuring that your design is correct. And I'm sure this is covered in lots of books (as well as google, as I said).
Sorry about that...i am designing it using cmos,n i had designed a JK latch before...i need a edge trigerred JK Flip Flop.
I need to design a 8-bit synchronous counter using CMOS, so i want to design an edge triggered JK Flip-Flop.
I got to know that MSJK work as edge triggered Flip-Flop so trying to design it...I have the gate level representation of MSJK n i need the CMOS representation of it...
Yes i had designed a JK Latch before...i was designing the flip flop using cmos and was a bit confused....
Now got a clear picture about it...
Anyways thank you for the Response.