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JK Flip Flop

Anand T

Hello Everyone,

 I am new to cadence and hav designed a JK FlipFlop.

I need to give a clock signal so that the inputs trigger only at the rising edge.

Now the outputs change for a change in input if the clock signal is high.

Its acting like an Edge triggered flipflop.

I want to know how to make the clock edge triggered.

I am implementing it in cadence virtuoso...Pls do help me out with this.

 

Thanks in advance.

Parents

  • Hi skillUser,

    Sorry about that...i am designing it using cmos,n i had designed a JK latch before...i need a edge trigerred JK Flip Flop.

    I need to design a 8-bit synchronous counter using CMOS, so i want to design an edge triggered JK Flip-Flop.

    I got to know that MSJK work as edge triggered Flip-Flop so trying to design it...I have the gate level representation of MSJK n i need the CMOS representation of it...

Reply

  • Hi skillUser,

    Sorry about that...i am designing it using cmos,n i had designed a JK latch before...i need a edge trigerred JK Flip Flop.

    I need to design a 8-bit synchronous counter using CMOS, so i want to design an edge triggered JK Flip-Flop.

    I got to know that MSJK work as edge triggered Flip-Flop so trying to design it...I have the gate level representation of MSJK n i need the CMOS representation of it...

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