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"freeing" nets in 6.1.x VXL

linbo

 Does anyone have any hints for "freeing" shapes and vias from their net connectivity in VXL 6.1.x?  It seems the sticky net problem from a long time ago is back.

 

Example:

 I have a via on a net named foo with an error marker.  If I query the via the net is vdd.  When I extract, the error marker remains and the error shape is still there and the via's net is still vdd.  Despite quitting out of Cadence session and restarting the dang via remains firmly connected to vdd.  It is clear that vdd is not involved in any way with the via or the net.

 The only way I can get the via to "free" it's net assignment is to copy the via to a second via, delete the first one and place the new copy onto the net named foo.   If I re-extract the net on the via is now foo.

 

If someone has some skill code out there that could fix this I would really appreciate it.  If you work for a company that wants the layouts to be "XL compliant" this is a real pain.

Parents
  • linbo

     Hi Andrew,

    There are problems with a service request:  It is difficult to get the tool to reproduce this one on cue.  It only happens after working on a cell for a long time.  I cannot send the company IP with the problem and so I wind up fiddling with a fake cell trying to get it to "break" for a test case; no time in a production environment.

    In the ancient past, where the sticky nets had lots of bugs there were some skill routines that would strip the nets and allow a fresh start.

    It would also help if VXL held pins as a firm starting point in an extract.  The example I described had a pin, a via, a metal 2, a pcell connection with the gate.  That's it.  No complex connections here and there.  Yet still, despite the pin's net (foo), the via remained vdd.

    I know this is getting a bit farther afield but it would be nice to have a push net feature where one could designate a net name and force propogation from that point.

Reply
  • linbo

     Hi Andrew,

    There are problems with a service request:  It is difficult to get the tool to reproduce this one on cue.  It only happens after working on a cell for a long time.  I cannot send the company IP with the problem and so I wind up fiddling with a fake cell trying to get it to "break" for a test case; no time in a production environment.

    In the ancient past, where the sticky nets had lots of bugs there were some skill routines that would strip the nets and allow a fresh start.

    It would also help if VXL held pins as a firm starting point in an extract.  The example I described had a pin, a via, a metal 2, a pcell connection with the gate.  That's it.  No complex connections here and there.  Yet still, despite the pin's net (foo), the via remained vdd.

    I know this is getting a bit farther afield but it would be nice to have a push net feature where one could designate a net name and force propogation from that point.

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