Pin order of a PMOS in layout cannot match with schematic

Hi Ali

Thank you for the excellent problem description. : )  Would you please try adding a swapPins expression as shown below and see if it helps in resolving the problem?

Best regards
Quek

 Thanks Quek for your reply and effort for showing the comment using a figure.

Here is the LVS report that is insensitive to the swapPins expression. It was tried with autoPinSwap (general) enabled and disabled. Also, pfet_m0(sch) has the same pinout as pfet_m1(lay). However, they are shown as unmatched instances.

========================================================================[inv1x]
====== Bad Initial Net Bindings (nets don't match) ============================
===============================================================================

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (badbind 1)
Schematic Net:  A
S      *1   of pfet_m0 G
S      *1   of nfet_m0 G

Layout Net:  A
L      *1   of nfet_m0 G
L      *1   of pfet_m1 ?G

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (badbind 2)
Schematic Net:  Y
S      *1   of pfet_m0 {D S}
S      *1   of nfet_m0 {D S}

Layout Net:  Y
L      *1   of nfet_m0 {D S}
L      *1   of pfet_m1 ?{S D}

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (badbind 3)
Schematic Net:  vddd!
S      *1   of pfet_m0 {D S}
S      *1   of pfet_m0 B

Layout Net:  vddd!
L      *1   of pfet_m1 ?{S D}
L      *1   of pfet_m1 ?B

========================================================================[inv1x]
====== Problem Schematic Nets (no exact match in layout) ======================
===============================================================================
S
S ?vddd!
S       1   of pfet_m0 {D S}
S       1   of pfet_m0 B
S
S ?Y
S       1   of pfet_m0 {D S}
S       1   of nfet_m0 {D S}
S
S ?A
S       1   of pfet_m0 G
S       1   of nfet_m0 G

========================================================================[inv1x]
====== Problem Layout Nets (no exact match in schematic) ======================
===============================================================================
L
L ?Y
L       1   of nfet_m0 {D S}
L       1   of pfet_m1 ?{S D}
L
L ?A
L       1   of nfet_m0 G
L       1   of pfet_m1 ?G
L
L ?vddd!
L       1   of pfet_m1 ?{S D}
L       1   of pfet_m1 ?B

========================================================================[inv1x]
====== Unmatched Schematic Instances ==========================================
===============================================================================

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (schinst 1)
Schematic Instance: T0  pfet_m0

S Pin        Net
S ---        ---
S D          Y
S G          A
S S          vddd!
S B          vddd!

========================================================================[inv1x]
====== Unmatched Layout Instances =============================================
===============================================================================

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (layinst 1)
Layout Instance:    avD172_1  pfet_m1

L Pin        Net
L ---        ---
L G          A
L S          vddd!
L D          Y
L B          vddd!

========================================================================[inv1x]
====== Summary of Errors ======================================================
===============================================================================

Schematic  Layout     Error Type
---------  ------     ----------
 3          3         Bad Initial Net Bindings
 1          1         Unmatched Instances

========================================================================
====File: inv1x.cps
========================================================================
                                                                              
; autoPinSwap() results for schematic network.


========================================================================
====File: inv1x.cfr
========================================================================
The LVS run "inv1x" has completed successfully.

Compare problems were detected in 1 cells.
   1 cells had device mismatches.
   1 cells had nets mismatches.
   0 cells matched

No Extraction Problems were detected.