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Pin order of a PMOS in layout cannot match with schematic

naderi

 Hello all,

I have a simple inverter, which has one NFET( multiplicity=1 ) and one PFET ( multiplicity=2) as shown in the attached figure .

I used virtuoso-XL to draw the layout and Assura for LVS and QRC.

Dispite of similar layout, Assura-QRC shows the pin order of two pfet trransistors are not match after extraction. The extracted sp netlist is :

MT1    Y    A    vssd!    vssd!    nfet    L=0.12U    W=0.16U ....
MavD172_1    vddd!    A    Y    vddd!    pfet    L=0.12U    W=0.16U ....
MavD172_2    Y    A    vddd!    vddd!    pfet    L=0.12U    W=0.16U .....

Rotating, or mirroring of the pfet in the layour cannot fix the problem. The problem causes LVS mismatch and cannot be fixed by changing the pin order in the schematic.

Why similar layouts are extracted differently, and is there any fix for that?

Thanks,

Ali

icfb.exe version 5.1.0 06/20/2007

sub-version 5.10.41_USR5.90.69

ASSURA sub-version 3.2_USR2, 2008-12-18-0841

Parents
  • Quek

    Hi Ali

    Thank you for the excellent problem description. : )  Would you please try adding a swapPins expression as shown below and see if it helps in resolving the problem?

    Best regards
    Quek

Reply
  • Quek

    Hi Ali

    Thank you for the excellent problem description. : )  Would you please try adding a swapPins expression as shown below and see if it helps in resolving the problem?

    Best regards
    Quek

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