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  3. Problem in importing CDL/Spice netlist ...?

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Problem in importing CDL/Spice netlist ...?

Prabhu The ICL
Prabhu The ICL over 14 years ago

 Hi! All,
  Once again I need your help. I am using Cadence IC514 version.
  I am trying to import a spice netlist using " CDL->Import " to make a corresponding schematic.
  I am able to import MOS transistors successfully but not capacitors & resistors.
  Here are the files that I am using for 'CDLIn' along with error output files ...
******************************

*******************************************************
FileName:- map.in
******************
devMap  := nfet nch
termMap := D D G G S S B B
propMap := w w m simM
addProp := model nch

devMap  := pfet pch
termMap := D D G G S S B B
propMap := w w m simM
addProp := model pch

devMap     := capacitor nmoscap_25
termMap := PLUS PLUS MINUS MINUS
propMap := c c
addProp := model nmoscap_25

devMap  := phyres rppolywo_m
termMap := PLUS PLUS MINUS MINUS SUB BULK
propMap := r res w sumW l sumL addProp := model rppolywo_m
*************************************************************************************
FileName:- test.sp
*******************
* SPICE NETLIST
***************************************
*.BIPOLAR
*.RESI = 2000
*.RESVAL
*.CAPVAL
*.DIOPERI
*.DIOAREA
*.EQUATION
*.SCALE METER
*.MEGA
.PARAM

***************************************
.SUBCKT nmoscap_25 PLUS MINUS
.ENDS
***************************************
.SUBCKT rnpolywo_m PLUS MINUS BULK
.ENDS
***************************************
.SUBCKT test vss vdd out
** N=3 EP=3 IP=0 FDC=2
X0 out vss nmoscap_25 lr=1e-06 wr=1e-06 $X=13640 $Y=900 $D=286
X1 vdd out vss rppolywo_m lr=1e-05 wr=2e-06 $X=770 $Y=450 $D=370
.ENDS
*************************************************************************************
FileName:- ni.log
*************************
############################################
Reference Libraries...
basic
analogLib
tsmcN65
test_bt2
###################################
---- Device-mapping enabled ----
3 subckt(s) found in the netlist file.
==========================
  Subckt: test
==========================
==========================
  Subckt: nmoscap_25
==========================
Created the CV nmoscap_25->netlist_tmp.
ERROR (CDLIN-44): The sub-circuit 'nmoscap_25' does not have any instance (box element). Hence, its
schematic view will not be prepared.
Usage error.
TERED    0 ERRORS (   5 WARNINGS) DURING FILE INPUT
 FILE :./RUNS/test.sp
 *** NUMBER OF ELEMENT BOXES DEFINED     :     2
*************************************************************************************
FileName:- ni.err
**************************
PROCESSING INPUT FILE: ./RUNS/test.sp
*** WARNING : *.EQUATION IS NOT SUPPORTED BY CDLIN. IGNORED
*/W* WARNING ***: NO ELEMENT INSIDE SUBCKT nmoscap_25 ** WARNING ** BOX NAME CAN NOT START WITH B,C,D,M,P,R AND CAN HAVE THREE CHARACTERS ONLY
*/W* WARNING ***: NO ELEMENT INSIDE SUBCKT rnpolywo_m ** WARNING ** BOX NAME CAN NOT START WITH B,C,D,M,P,R AND CAN HAVE THREE CHARACTERS ONLY

 FILE :./RUNS/test.sp
 *** NUMBER OF ELEMENT BOXES DEFINED     :     2
*************************************************************************************

I hope this information is apropos.
Please, Can someone guide me to resolve this issue.


Thanks in Advance ...
 
--
Prabhakar. K
IC Layout Engineer
SoCtronics Tech. Pvt. Ltd.
e-mail: prabhu.usic@gmail.com
---
(-: 'GOAL' : Perhaps there's more than one way to reach it :-) 

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Parents
  • Prabhu The ICL
    Prabhu The ICL over 14 years ago
    Hi! Quek,
    As you suggested I made the modifications to the
    netlist. All is going fine except when there are 2-terminal & 3-termianl
    resistors exist.
    If I use the same prefix (i.e. R) for both the devices CDLIN translating
    only 2-terminal device for both the statements.
    I mean ... consider the following two statements ...

    R0 vdd out vss rppolywo_m lr=1e-05 wr=2e-06 (==> 3-terminal res)
    R1 net1 net2 rppolywo l=1e-05 w=2e-06 (==> 2-terminal res)

    For the above two statements I am getting 'rppolywo' device.
    In addition to this issue can you clear me for one more issue .. If you
    don't mind ...!
    How to translate different types of MOS devices ...?
    Suppose, If I have pch, pch_mac, pch_25_mac etc .. devices which
    corresponds to model 'nfet' , How to write map file in this case. I mean
    how to
    differentiate them with prop 'subType' ...?



    --
    Thanks & Regards
    ---
    Prabhakar. K
    IC Layout Engineer
    SoCtronics Tech. Pvt. Ltd.
    Hyderabad-INDIA
    e-mail: prabhu.usic@gmail.com
    -
    (-: 'GOAL' : Perhaps there's more than one way to reach it :-)
    • Cancel
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  • Prabhu The ICL
    Prabhu The ICL over 14 years ago
    Hi! Quek,
    As you suggested I made the modifications to the
    netlist. All is going fine except when there are 2-terminal & 3-termianl
    resistors exist.
    If I use the same prefix (i.e. R) for both the devices CDLIN translating
    only 2-terminal device for both the statements.
    I mean ... consider the following two statements ...

    R0 vdd out vss rppolywo_m lr=1e-05 wr=2e-06 (==> 3-terminal res)
    R1 net1 net2 rppolywo l=1e-05 w=2e-06 (==> 2-terminal res)

    For the above two statements I am getting 'rppolywo' device.
    In addition to this issue can you clear me for one more issue .. If you
    don't mind ...!
    How to translate different types of MOS devices ...?
    Suppose, If I have pch, pch_mac, pch_25_mac etc .. devices which
    corresponds to model 'nfet' , How to write map file in this case. I mean
    how to
    differentiate them with prop 'subType' ...?



    --
    Thanks & Regards
    ---
    Prabhakar. K
    IC Layout Engineer
    SoCtronics Tech. Pvt. Ltd.
    Hyderabad-INDIA
    e-mail: prabhu.usic@gmail.com
    -
    (-: 'GOAL' : Perhaps there's more than one way to reach it :-)
    • Cancel
    • Vote Up 0 Vote Down
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