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  3. Problem in importing CDL/Spice netlist ...?

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Problem in importing CDL/Spice netlist ...?

Prabhu The ICL
Prabhu The ICL over 14 years ago

 Hi! All,
  Once again I need your help. I am using Cadence IC514 version.
  I am trying to import a spice netlist using " CDL->Import " to make a corresponding schematic.
  I am able to import MOS transistors successfully but not capacitors & resistors.
  Here are the files that I am using for 'CDLIn' along with error output files ...
******************************

*******************************************************
FileName:- map.in
******************
devMap  := nfet nch
termMap := D D G G S S B B
propMap := w w m simM
addProp := model nch

devMap  := pfet pch
termMap := D D G G S S B B
propMap := w w m simM
addProp := model pch

devMap     := capacitor nmoscap_25
termMap := PLUS PLUS MINUS MINUS
propMap := c c
addProp := model nmoscap_25

devMap  := phyres rppolywo_m
termMap := PLUS PLUS MINUS MINUS SUB BULK
propMap := r res w sumW l sumL addProp := model rppolywo_m
*************************************************************************************
FileName:- test.sp
*******************
* SPICE NETLIST
***************************************
*.BIPOLAR
*.RESI = 2000
*.RESVAL
*.CAPVAL
*.DIOPERI
*.DIOAREA
*.EQUATION
*.SCALE METER
*.MEGA
.PARAM

***************************************
.SUBCKT nmoscap_25 PLUS MINUS
.ENDS
***************************************
.SUBCKT rnpolywo_m PLUS MINUS BULK
.ENDS
***************************************
.SUBCKT test vss vdd out
** N=3 EP=3 IP=0 FDC=2
X0 out vss nmoscap_25 lr=1e-06 wr=1e-06 $X=13640 $Y=900 $D=286
X1 vdd out vss rppolywo_m lr=1e-05 wr=2e-06 $X=770 $Y=450 $D=370
.ENDS
*************************************************************************************
FileName:- ni.log
*************************
############################################
Reference Libraries...
basic
analogLib
tsmcN65
test_bt2
###################################
---- Device-mapping enabled ----
3 subckt(s) found in the netlist file.
==========================
  Subckt: test
==========================
==========================
  Subckt: nmoscap_25
==========================
Created the CV nmoscap_25->netlist_tmp.
ERROR (CDLIN-44): The sub-circuit 'nmoscap_25' does not have any instance (box element). Hence, its
schematic view will not be prepared.
Usage error.
TERED    0 ERRORS (   5 WARNINGS) DURING FILE INPUT
 FILE :./RUNS/test.sp
 *** NUMBER OF ELEMENT BOXES DEFINED     :     2
*************************************************************************************
FileName:- ni.err
**************************
PROCESSING INPUT FILE: ./RUNS/test.sp
*** WARNING : *.EQUATION IS NOT SUPPORTED BY CDLIN. IGNORED
*/W* WARNING ***: NO ELEMENT INSIDE SUBCKT nmoscap_25 ** WARNING ** BOX NAME CAN NOT START WITH B,C,D,M,P,R AND CAN HAVE THREE CHARACTERS ONLY
*/W* WARNING ***: NO ELEMENT INSIDE SUBCKT rnpolywo_m ** WARNING ** BOX NAME CAN NOT START WITH B,C,D,M,P,R AND CAN HAVE THREE CHARACTERS ONLY

 FILE :./RUNS/test.sp
 *** NUMBER OF ELEMENT BOXES DEFINED     :     2
*************************************************************************************

I hope this information is apropos.
Please, Can someone guide me to resolve this issue.


Thanks in Advance ...
 
--
Prabhakar. K
IC Layout Engineer
SoCtronics Tech. Pvt. Ltd.
e-mail: prabhu.usic@gmail.com
---
(-: 'GOAL' : Perhaps there's more than one way to reach it :-) 

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  • Prabhu The ICL
    Prabhu The ICL over 14 years ago
    Hi! Quek,
    I have succeeded in translating different type of MOS
    devices as you described ...
    But regarding resistors, I am keep getting the same issue ... In my case
    resistors in cdl netlist doesn't contain 'r' value .. So I can't import
    them using
    'r' value ... I tried to match other properties but in vain ... Is there
    any alternative to this ...
    Please, consider the following cdl netlist & dev-map files for your
    reference ...
    ************************************************************
    *.BIPOLAR
    *.RESI = 2000
    *.RESVAL
    *.CAPVAL
    *.DIOPERI
    *.DIOAREA
    *.EQUATION
    *.SCALE METER
    *.MEGA
    .PARAM

    .SUBCKT rppolywo_m PLUS MINUS BULK
    .ENDS

    .SUBCKT rppolywo PLUS MINUS
    .ENDS

    .SUBCKT nmoscap_25 PLUS MINUS
    .ENDS

    .SUBCKT test1 I Y gnd vdd
    *.PININFO I:I gnd:I vdd:I Y:O
    CC1 net022 gnd nmoscap_25 lr=1u wr=1u m=1
    CC0 net024 gnd nmoscap_25 lr=1u wr=1u m=1
    RR1 net9 net022 gnd rppolywo_m lr=20u wr=2u m=1 mf=1 mismatchflag=0
    RR0 net5 net024 rppolywo l=10u w=2u m=1
    MM5 net5 I gnd gnd NM l=60n w=200n m=1
    MM4 net9 net5 gnd gnd NV l=60n w=200n m=1
    MM3 Y net9 gnd gnd NH l=280n w=400n m=1
    MM2 Y net9 vdd vdd PH l=280n w=400n m=1
    MM1 net9 net5 vdd vdd PV l=60n w=200n m=1
    MM0 net5 I vdd vdd PM l=60n w=200n m=1
    .ENDS
    ************************************************************
    devMap := nfet nch
    propMatch := subType NM
    termMap := D D G G S S B B
    propMap := m simM
    addProp := model nch

    devMap := nfet nch_mac
    propMatch := subType NV
    termMap := D D G G S S B B
    propMap := m simM
    addProp := model nch_mac

    devMap := nfet nch_25
    propMatch := subType NH
    termMap := D D G G S S B B
    propMap := m simM
    addProp := model nch_25

    devMap := pfet pch
    propMatch := subType PM
    termMap := D D G G S S B B
    propMap := m simM
    addProp := model pch

    devMap := pfet pch_mac
    propMatch := subType PV
    termMap := D D G G S S B B
    propMap := m simM
    addProp := model pch_mac

    devMap := pfet pch_25
    propMatch := subType PH
    termMap := D D G G S S B B
    propMap := m simM
    addProp := model pch_25

    devMap := capacitor nmoscap_25
    termMap := PLUS PLUS MINUS MINUS
    propMap := c c
    addProp := model nmoscap_25

    devMap := resistor rppolywo
    termMap := PLUS PLUS MINUS MINUS
    propMap := r res w w l l
    addProp := model rppolywo

    devMap := phyres rppolywo_m
    termMap := PLUS PLUS MINUS MINUS SUB BULK
    propMap := r res w w l l
    addProp := model rppolywo_m
    ************************************************************


    --
    Thanks & Regards
    ---
    Prabhakar. K
    IC Layout Engineer
    SoCtronics Tech. Pvt. Ltd.
    Hyderabad - INDIA
    e-mail: prabhu.usic@gmail.com
    -
    (-: 'GOAL' : Perhaps there's more than one way to reach it :-)
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  • Prabhu The ICL
    Prabhu The ICL over 14 years ago
    Hi! Quek,
    I have succeeded in translating different type of MOS
    devices as you described ...
    But regarding resistors, I am keep getting the same issue ... In my case
    resistors in cdl netlist doesn't contain 'r' value .. So I can't import
    them using
    'r' value ... I tried to match other properties but in vain ... Is there
    any alternative to this ...
    Please, consider the following cdl netlist & dev-map files for your
    reference ...
    ************************************************************
    *.BIPOLAR
    *.RESI = 2000
    *.RESVAL
    *.CAPVAL
    *.DIOPERI
    *.DIOAREA
    *.EQUATION
    *.SCALE METER
    *.MEGA
    .PARAM

    .SUBCKT rppolywo_m PLUS MINUS BULK
    .ENDS

    .SUBCKT rppolywo PLUS MINUS
    .ENDS

    .SUBCKT nmoscap_25 PLUS MINUS
    .ENDS

    .SUBCKT test1 I Y gnd vdd
    *.PININFO I:I gnd:I vdd:I Y:O
    CC1 net022 gnd nmoscap_25 lr=1u wr=1u m=1
    CC0 net024 gnd nmoscap_25 lr=1u wr=1u m=1
    RR1 net9 net022 gnd rppolywo_m lr=20u wr=2u m=1 mf=1 mismatchflag=0
    RR0 net5 net024 rppolywo l=10u w=2u m=1
    MM5 net5 I gnd gnd NM l=60n w=200n m=1
    MM4 net9 net5 gnd gnd NV l=60n w=200n m=1
    MM3 Y net9 gnd gnd NH l=280n w=400n m=1
    MM2 Y net9 vdd vdd PH l=280n w=400n m=1
    MM1 net9 net5 vdd vdd PV l=60n w=200n m=1
    MM0 net5 I vdd vdd PM l=60n w=200n m=1
    .ENDS
    ************************************************************
    devMap := nfet nch
    propMatch := subType NM
    termMap := D D G G S S B B
    propMap := m simM
    addProp := model nch

    devMap := nfet nch_mac
    propMatch := subType NV
    termMap := D D G G S S B B
    propMap := m simM
    addProp := model nch_mac

    devMap := nfet nch_25
    propMatch := subType NH
    termMap := D D G G S S B B
    propMap := m simM
    addProp := model nch_25

    devMap := pfet pch
    propMatch := subType PM
    termMap := D D G G S S B B
    propMap := m simM
    addProp := model pch

    devMap := pfet pch_mac
    propMatch := subType PV
    termMap := D D G G S S B B
    propMap := m simM
    addProp := model pch_mac

    devMap := pfet pch_25
    propMatch := subType PH
    termMap := D D G G S S B B
    propMap := m simM
    addProp := model pch_25

    devMap := capacitor nmoscap_25
    termMap := PLUS PLUS MINUS MINUS
    propMap := c c
    addProp := model nmoscap_25

    devMap := resistor rppolywo
    termMap := PLUS PLUS MINUS MINUS
    propMap := r res w w l l
    addProp := model rppolywo

    devMap := phyres rppolywo_m
    termMap := PLUS PLUS MINUS MINUS SUB BULK
    propMap := r res w w l l
    addProp := model rppolywo_m
    ************************************************************


    --
    Thanks & Regards
    ---
    Prabhakar. K
    IC Layout Engineer
    SoCtronics Tech. Pvt. Ltd.
    Hyderabad - INDIA
    e-mail: prabhu.usic@gmail.com
    -
    (-: 'GOAL' : Perhaps there's more than one way to reach it :-)
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