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  3. Problem in importing CDL/Spice netlist ...?

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Problem in importing CDL/Spice netlist ...?

Prabhu The ICL
Prabhu The ICL over 14 years ago

 Hi! All,
  Once again I need your help. I am using Cadence IC514 version.
  I am trying to import a spice netlist using " CDL->Import " to make a corresponding schematic.
  I am able to import MOS transistors successfully but not capacitors & resistors.
  Here are the files that I am using for 'CDLIn' along with error output files ...
******************************

*******************************************************
FileName:- map.in
******************
devMap  := nfet nch
termMap := D D G G S S B B
propMap := w w m simM
addProp := model nch

devMap  := pfet pch
termMap := D D G G S S B B
propMap := w w m simM
addProp := model pch

devMap     := capacitor nmoscap_25
termMap := PLUS PLUS MINUS MINUS
propMap := c c
addProp := model nmoscap_25

devMap  := phyres rppolywo_m
termMap := PLUS PLUS MINUS MINUS SUB BULK
propMap := r res w sumW l sumL addProp := model rppolywo_m
*************************************************************************************
FileName:- test.sp
*******************
* SPICE NETLIST
***************************************
*.BIPOLAR
*.RESI = 2000
*.RESVAL
*.CAPVAL
*.DIOPERI
*.DIOAREA
*.EQUATION
*.SCALE METER
*.MEGA
.PARAM

***************************************
.SUBCKT nmoscap_25 PLUS MINUS
.ENDS
***************************************
.SUBCKT rnpolywo_m PLUS MINUS BULK
.ENDS
***************************************
.SUBCKT test vss vdd out
** N=3 EP=3 IP=0 FDC=2
X0 out vss nmoscap_25 lr=1e-06 wr=1e-06 $X=13640 $Y=900 $D=286
X1 vdd out vss rppolywo_m lr=1e-05 wr=2e-06 $X=770 $Y=450 $D=370
.ENDS
*************************************************************************************
FileName:- ni.log
*************************
############################################
Reference Libraries...
basic
analogLib
tsmcN65
test_bt2
###################################
---- Device-mapping enabled ----
3 subckt(s) found in the netlist file.
==========================
  Subckt: test
==========================
==========================
  Subckt: nmoscap_25
==========================
Created the CV nmoscap_25->netlist_tmp.
ERROR (CDLIN-44): The sub-circuit 'nmoscap_25' does not have any instance (box element). Hence, its
schematic view will not be prepared.
Usage error.
TERED    0 ERRORS (   5 WARNINGS) DURING FILE INPUT
 FILE :./RUNS/test.sp
 *** NUMBER OF ELEMENT BOXES DEFINED     :     2
*************************************************************************************
FileName:- ni.err
**************************
PROCESSING INPUT FILE: ./RUNS/test.sp
*** WARNING : *.EQUATION IS NOT SUPPORTED BY CDLIN. IGNORED
*/W* WARNING ***: NO ELEMENT INSIDE SUBCKT nmoscap_25 ** WARNING ** BOX NAME CAN NOT START WITH B,C,D,M,P,R AND CAN HAVE THREE CHARACTERS ONLY
*/W* WARNING ***: NO ELEMENT INSIDE SUBCKT rnpolywo_m ** WARNING ** BOX NAME CAN NOT START WITH B,C,D,M,P,R AND CAN HAVE THREE CHARACTERS ONLY

 FILE :./RUNS/test.sp
 *** NUMBER OF ELEMENT BOXES DEFINED     :     2
*************************************************************************************

I hope this information is apropos.
Please, Can someone guide me to resolve this issue.


Thanks in Advance ...
 
--
Prabhakar. K
IC Layout Engineer
SoCtronics Tech. Pvt. Ltd.
e-mail: prabhu.usic@gmail.com
---
(-: 'GOAL' : Perhaps there's more than one way to reach it :-) 

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  • Quek
    Quek over 14 years ago

    Hi Prabhakar

    That's great. You are welcome. : )

    Best regards
    Quek

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  • Quek
    Quek over 14 years ago

    Hi Prabhakar

    That's great. You are welcome. : )

    Best regards
    Quek

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