incorrect extraction issue

I am working with Virtuoso version IC6.1.3.500.13 and mentor 2011 (also have access to older versions and have previously used 2009). The pdk I am working with apparently has a known bug (confirmed by the foundry) such that the extracted transistors are always incorrect - instead of a 10 finger fet with total width 8um, for example, the tool extracts 10 transistors, 1 finger each, EACH with a width of 8 um. does anyone have any suggestions on how to manually fix this so i can run simulations on the extracted circuits using the config view? I have tried 1. manually editing the calibre view to ensure the correct width for each fet - i then get the error Error (OSSHNL-109) : the cell view, [name of calibre view], has been modified since the extraction. Re-extract the design (File->Check and Save menu option) for schematic cell views to correct this error. 2. copying and pasting extracted circuit to a schematic view - i then get the error ERROR (ADE-6026): Unable to create the netlist due to failure of the following operating system command "cat: ihnl/cds1/netlist: No such file or directory". Thanks.