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incorrect extraction issue

kristen
I am working with Virtuoso version IC6.1.3.500.13 and mentor 2011 (also have access to older versions and have previously used 2009). The pdk I am working with apparently has a known bug (confirmed by the foundry) such that the extracted transistors are always incorrect - instead of a 10 finger fet with total width 8um, for example, the tool extracts 10 transistors, 1 finger each, EACH with a width of 8 um. does anyone have any suggestions on how to manually fix this so i can run simulations on the extracted circuits using the config view? I have tried 1. manually editing the calibre view to ensure the correct width for each fet - i then get the error Error (OSSHNL-109) : the cell view, [name of calibre view], has been modified since the extraction. Re-extract the design (File->Check and Save menu option) for schematic cell views to correct this error. 2. copying and pasting extracted circuit to a schematic view - i then get the error ERROR (ADE-6026): Unable to create the netlist due to failure of the following operating system command "cat: ihnl/cds1/netlist: No such file or directory". Thanks.

  • Hi kristen

    Thank you very much for the detail explanation. Editing the extracted view manually would always result in "check and save" errors during netlisting. If the extracted view was created using QRC, we can add a callProc.il skillscript in the QRC tech directory to correct the extracted view. When QRC is generating the extracted view, it will read in callProc.il file and pass the cellview ID of the extracted view the script. The script can then search for the appropriate fet and modify its properties.

    Unfortunately, your extracted view has been generated using Calibre xRC and hence callProc.il method does not apply. I think it would be better for you to also post your question on Mentor Calibre forum to see if you can get more ideas. If it is ok with you, kindly update this thread with a link to your post on the Mentor forum so that everybody can benefit from your experience. : ) Thanks.

    Actually I think the Calibre LVS deck should be corrected to fix this problem. : )  The problem lies with the rule deck and not with extracted view generation. So modifying the extracted view is just a workaround.

    A 3rd possible workaround is as follows:
    a. Generate a spice netlist using Calibre xRC
    b. Use a text editor to correct the fet properties
    c. Create a symbol in Virtuoso to represent the netlist and simulate the netlist directly


    Best regards
    Quek

  • Hi quek -

    thanks, i have been exploring this work around. oddly enough when i do a spectre extraction (instead of extracting to calibreView) the FETs extract correctly. however, when i try to use the spectre view in my simulations (i'm referencing some Cadence help documentation, the "Virtuoso Analog Design Environment L User Guide", and some posts i found on other forums - one which you replied to some time ago, i believe) - the simulator thinks it's a spice file and says i should change the file to indicate that the language is spice, but when i change the language indicator from spectre to spice it says the correct language is actually spectre. do you have any tips on this?

  • Hi Kristen

    It is possible to run into problems only when generating extracted views and not spectre or spice netlists. This is because when generating extracted view, the device parameters in the parasitic netlist has to match that of the device CDF. E.g. LVS deck extracts a parameter named "W=123u" for fetABC and passes it to QRC(or Calibre xRC). QRC will simply use this parameter when creating the extracted view. But if the CDF info of fetABC is actually looking for a parameter named "width", it will not accept "W" from QRC and will use default value of "width" from CDF. This situation is possible because some pdks do additional mapping from "width" to "w" in CDF.

    (CDF : Component Description Format)

    Hence a wrong extracted view will be generated. But if we were to simply use a spice/spectre netlist with "W" and not "width", it would simulate well because "W" is what the model file needs.

    In the spectre parasitic netlist which you had obtained using Calibre xRC, does it has "simulator lang=spectre" as the 1st line? Is the file named with extension ".sp" instead of ".scs"? It should be named as ".scs".


    Best regards
    Quek

  • Hi Quek,

    thanks again for your reply. I was mistaken, the issue is in my input.scs file - but my guess is it's not reading my extracted.scs file correctly?

    the error I get, when i use either a symbol view or spectre view of the subckt, is : ERROR(SFE-678) "input.scs" 15: statement is not in spectre form. use 'simulator lang=spice' to introduce spice language sections.

    the line in question is:
    I5 (0 net4 net2 net28) my_subckt

    when i use a different view i noticed that the subckt netlist is basically incorporated into the input.scs netlist, but this is not the case with my extracted subckt. the extension of my extracted netlist is .scs. should i be using the spice netlist reader (spp)? i had seen it mentioned on a forum but when i try to use this, i get an error "unable to run circuit preprocessor. illegal seek". i'm not sure if this is an error with the cadence installation or something else.

    Thanks for all your help, I really appreciate it.
  • Hi Kristen

    I am not very sure why this is happening so perhaps we should go through it step-by-step. Would you please check if this is how you are doing the simulation?

    a. Run Calibre xRC to generate a parasitic netlist in spectre format. File is named as myFile.scs. Ensure that "simulator lang=spectre" is the first line. E.g.

    simulator lang=spectre
    subckt ABC p1 p2 p3 ...

    b. Create a symbol named myCell with pins p1, p2, p3, ... as listed in subckt line of myFile.scs
    c. Copy symbol view of myCell as spectre view
    d. Edit CDF spectre simInfo of myCell so that "componentName" is the name of the subckt ABC in myFile.scs
    e. Ensure that pin order listed in simInfo section is the same as that of the subckt in myFile.scs
    f. Instantiate the symbol in a schematic and add the necessary input sources, etc
    g. Open up ADE-L and do spectre simulation

    Best regards
    Quek
  • Hi quek,

    thanks again for your reply. i have the same error as i did before, after following your procedure.

    some quick clarifications though, do i instantiate the symbol view or the spectre view? i tried both with both yielding the same results.

    i also noted that changing the model name in the cdf to an incorrect name doesn't change my input.scs, so apparently the simulator isn't even reading the input file in, it's just seeing that there is a subcircuit there because I placed a block in the schematic view. any thoughts on this?


    Kristen

  • Hi Kristen

    You should use the symbol view. Would you please check the following?

    a. Has the spectre netlist been added as one of the model files in ADE-L?

    b. Please execute the following in ciw and check the return value:
    getShellEnvVar("CDS_Netlisting_Mode")

    c. Please upload a snapshot of "spectre" siminfo cdf section


    Thanks
    Quek

  • Quek, a. yes, i have added the .scs file as a model file. b. it is "Analog". c. see attached. Thanks,

  • Hi Kristen

    Would you please check the following?

    a. In ADE-L netlist, does the line for the cell look similar to the following?

    I5 (net1 net2 net3 net4) 100GHz_half_backup

    If not, how does it look like?

    b. Please go to "Setup->Environment". What are the values for "Switch View List" and "Stop View list"?

    c. Would you please execute the following cmd in ciw and paste the output?

    ddGetObj("Osc_layouts" "100GHz_half_backup")~>views~>name



    Thanks
    Quek

  • Quek,

    a. the line is I6 (0 net4 net2 net28) 100GHz_half_backup
    which looks correct to me. however when i put in a different subcell (like if i make a schematic and put the symbol view in, the input.scs is populated with the model file).

    b. the switchview list is: spectre cmos_sch cmos.sch schematic veriloga
    the stopview list is: spectre

    c. the command gives the following: ("spectre" "schematic" "layout" "symbol") which matches the views i have in the library manager.

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