Can't create devices in layout using pycells

Hi Eddie

Thank you for the good description of the problem. : )  Unfortunately we do not support pycells. It would be best for you to use SKILL pcells in your layout. Sorry that this answer is not what you are looking for but it is the best way to resolve the problem.

Best regards
Quek

Does your PDK require Environment-Variables like e.g LD_LIBRARY_PATH for the python?

If so make sure to have the correct settings. Also take care for 32/64 bit issues.

You can use  the command :  layout -debug3264

to see what will be launched and if this matches your settings. 

regards, Uli

Thanks for your input.  Yes, the LD_LIBRARY_PATH variable must be set, and I

have done so according to the README file.  Your suggestion of using the -debug3264

was very useful. So far I do not have a solution to my issue, though.

One thing I did notice in rereading the documentation is that it "appears to me" that

Cadence uses a tcl callback to create the Pycell.?  Maybe this needs to be setup as well?

I am fairly proficient in skill, but this new iPDK format has got me confused and Cadence

support is minimal.  Maybe if everything wasn't encrypted, it would be easier to debug :)

Thanks,

Eddie

Eddie,

As Quek said, Cadence does not support the use of Pycells. What that means is that if there is a problem, we are unable to support or fix problems because we will not be able to reproduce the problem (unless it can be reproduced with a SKILL pcell), there is no testing, and also there are some features of the layout tools (primarily in VLS GXL) which require SKILL pcells. If you're using an "iPDK" then you should be able to get a version of the PDK from the foundry which uses SKILL pcells and thus does not have any of these problems or limitations.

You say that "Cadence uses a tcl callback". Well, Cadence does not use tcl callbacks, but maybe the Pycell-based PDK uses Tcl somewhere - I can't comment on that.

Regards,

Andrew.

Andrew,

 Thanks for your feedback.  I finally resolved the issue basically by 1) reading EVERYTHING I could from the

foundary, Cadence and Ciranova's website and 2) pure chance. Here is what I did for future reference.

1) Unzipped 2 imbedded files inside the Pycell directory that contained the layout information.  I could find

no documentation saying this was necessary and the directory was supposed to be 'self-extracting'.  Why these

are missed is a mystery.

 2) ALL applications' bit formats (linux, Cadence and Python) MUST agree.  All either 32bit or 64bit.  If any one

is off, Cadence device creation just fails with no discernable Warning or Error message.

And that's it.  I'm up and running.

Thanks again,

Eddie