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iPDK from TSMC 28nm pcell problems

Luc Laeveren

Hi,

We're having difficulties with the usage of the two TMSC 28nm iPDK's in Cadence:

iPDK_CRN28HPL_v0.3_2a_20110715_all.tar.gz and t-n28-cr-sp-003-w1_1_0b_20110620.zip

During instantiating of a PCELL in layout XL we get following warning:
*WARNING* (DB-220704): The Pcell super master: tsmcN28/nch_mac/layout is not a SKILL super master.The usage of non-SKILL Pcells in Virtuoso is not a supported feature.

Though it's only a warning, no layout is created, only a red square is visible on the layout screen.

The installation went without any problem and we're using the exact same tool version as TSMC states in the Releasenotes;

Program:        @(#)$CDS: virtuoso version 6.1.4-64b 08/02/2010 00:21 (sjfnl002) $
Sub version:        sub-version  IC6.1.4-64b.500.6  (64-bit addresses)

I presume this has something to do with the phycells vs skill pcells? Do I need additional installation scripts or tools?

Parents
  • JukeBox
    Hi, I am using SKILL based pcells.There are two things that I would like to clarify.Firstly,I am not able to instantiate the layouts of any cell.I don't think that should happen.Secondly,if I try to change the 'w' or 'l' of any MOS , the changes are not being reflected in the schematic.What am I missing?
Reply
  • JukeBox
    Hi, I am using SKILL based pcells.There are two things that I would like to clarify.Firstly,I am not able to instantiate the layouts of any cell.I don't think that should happen.Secondly,if I try to change the 'w' or 'l' of any MOS , the changes are not being reflected in the schematic.What am I missing?
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