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How to make a unique name for verilog output?

naderi

 Hi all,

 I am using IC 6.1.4 (Cadence, ADE-XL) and have a verilogA block to write signals into a file. The problem is when the testbench is run over difference corners (process and design corncer) output file name of that verilog block does not change accordingly and therefore all the data are over-written.

 I am producing the output file as following:

         fileID = $fopen( "/sim/%C:t:r_%I.dat","w");

Is there any way to make the names unique as the corners changing?

Thanks,

Ali

Parents

  • Hi Ali,

    Does the process id change from one simulation corner to the next, or are they performed under the same simulator session? If the process id changes then you could use %P in the filename to involve the process id to make the filename more unique (this is not a guarantee of uniqueness, however, since process id's are re-used). I have tried to see if a (pseudo-)random number could be inserted in the filename, but I cannot see how to do this (I could not find an equivalent of the "sprintf" command, for example).

    Hope this may help,

    Regards,

    Lawrence.

     

Reply

  • Hi Ali,

    Does the process id change from one simulation corner to the next, or are they performed under the same simulator session? If the process id changes then you could use %P in the filename to involve the process id to make the filename more unique (this is not a guarantee of uniqueness, however, since process id's are re-used). I have tried to see if a (pseudo-)random number could be inserted in the filename, but I cannot see how to do this (I could not find an equivalent of the "sprintf" command, for example).

    Hope this may help,

    Regards,

    Lawrence.

     

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