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How to make a unique name for verilog output?

naderi

 Hi all,

 I am using IC 6.1.4 (Cadence, ADE-XL) and have a verilogA block to write signals into a file. The problem is when the testbench is run over difference corners (process and design corncer) output file name of that verilog block does not change accordingly and therefore all the data are over-written.

 I am producing the output file as following:

         fileID = $fopen( "/sim/%C:t:r_%I.dat","w");

Is there any way to make the names unique as the corners changing?

Thanks,

Ali

  • Hi Ali,

    Does the process id change from one simulation corner to the next, or are they performed under the same simulator session? If the process id changes then you could use %P in the filename to involve the process id to make the filename more unique (this is not a guarantee of uniqueness, however, since process id's are re-used). I have tried to see if a (pseudo-)random number could be inserted in the filename, but I cannot see how to do this (I could not find an equivalent of the "sprintf" command, for example).

    Hope this may help,

    Regards,

    Lawrence.

     

  • Hi Ali,

    Look at the "%D" and "%T" formatting commands for Date and Time respectively - these combined with the Process id (%P as noted above) and/or the Hostname (%H command) is likely to generate a unique filename. [Thanks to Andrew for the pointer to these]

    Hopefully this will help you achieve your goal.

    Regards,

    Lawrence.

  •  Dear Lawrence

    Thanks for your solution. I believe different process IDs should be enough for my simulations. However, I have already used all licenses of spectre and now waiting to finish simulations. Then I can verify your solution. I will come back in two days to update the post.

    Best Regards,

    Ali

  •  Thanks  Lawrence,

    It worked fine using %P.

    Best,

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