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How to make a unique name for verilog output?

naderi

 Hi all,

 I am using IC 6.1.4 (Cadence, ADE-XL) and have a verilogA block to write signals into a file. The problem is when the testbench is run over difference corners (process and design corncer) output file name of that verilog block does not change accordingly and therefore all the data are over-written.

 I am producing the output file as following:

         fileID = $fopen( "/sim/%C:t:r_%I.dat","w");

Is there any way to make the names unique as the corners changing?

Thanks,

Ali

Parents

  • Hi Ali,

    Look at the "%D" and "%T" formatting commands for Date and Time respectively - these combined with the Process id (%P as noted above) and/or the Hostname (%H command) is likely to generate a unique filename. [Thanks to Andrew for the pointer to these]

    Hopefully this will help you achieve your goal.

    Regards,

    Lawrence.

Reply

  • Hi Ali,

    Look at the "%D" and "%T" formatting commands for Date and Time respectively - these combined with the Process id (%P as noted above) and/or the Hostname (%H command) is likely to generate a unique filename. [Thanks to Andrew for the pointer to these]

    Hopefully this will help you achieve your goal.

    Regards,

    Lawrence.

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