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mixed signal SpectreVerilog simulation

isazulkc

Hi,

I'm trying to simulate a top level mixed-signal circuit with SpectreVerilog. The analog/digital partitioning succeed. However, because I use the same power and ground for the digital and analog parts, simulation fails and I get this error:

"  net vdd! ... is a nonsupply global net that is also an interface net. Interface element is not generated for this net. You should use separate analog and digital stimuli for this net or classify the net as a supply (power or ground) net "

How to classify a net as supply if I don't whant to use separate power net for analog and digital blocks ?

Thanks !!

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