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Does PNOISE sim of a sample & hold circuit include clock jitter effect?

peter6g

I'm doing a time domain PNOISE sim of a sample and hold circuit with clock buffers.  Do the noise results include clock jitter due to the clock buffers?

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  • peter6g

    Hi Andrew,

     But since the sampling clock thru the clock buffers "holds" the output of the sample and hold circuit, doens't jitter change the PSS result of the held output voltage?  It seems that sampling clock jitter and its effect of causing the held output voltage value to change is antithetic to what PSS is about, which is to converge to a periodic steady state solution.  And if what I've said is correct, then PNOISE would not account for the error voltage caused by clock jitter at the output of the sample and hold circuit. 

     Thanks.

    Peter

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  • peter6g

    Hi Andrew,

     But since the sampling clock thru the clock buffers "holds" the output of the sample and hold circuit, doens't jitter change the PSS result of the held output voltage?  It seems that sampling clock jitter and its effect of causing the held output voltage value to change is antithetic to what PSS is about, which is to converge to a periodic steady state solution.  And if what I've said is correct, then PNOISE would not account for the error voltage caused by clock jitter at the output of the sample and hold circuit. 

     Thanks.

    Peter

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