Stats

  • Locked Locked
  • Replies 10
  • Subscribers 126
  • Views 21302
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Importing verilog to Cadence schematic

Wonyoung

Hello,

I am trying to import a very simple verilog code containing one latch into Cadence using Import -> Verilog on CIW. I get the following error message.

INFO (VERILOGIN_GUI-13): Verilog Import process has started ...
ERROR (VERILOGIN-205): An internal memory error has occurred. Exiting.
INFO (VERILOGIN_GUI-15): Verilog Import completed. Look at logfile, ./verilogIn.log, for process execution details.

There is nothing in the logfile and I have enough memory. I am using IC6.1.5. Any help is appreciated!

Wonyoung
Parents
  • At the same time, I am trying to see if using "verilog2oa" and "conn2sch" can import verilog to Cadence schematic using the following commands.

    verilog2oa -verilog "./myverilog.syn.v" -top "myverilog" -lib "test" -view "netlist" -tieHigh VDD -tieLow VSS -overwrite

    conn2sch -lib test -cell myverilog -view netlist -destlib test -destview schematic -verbose -param conn2sch.conf

    When I run conn2sch, it complains that "ERROR (CONN2SCH-193): Instance XXX is not bound to any master.". I was wondering if you have any recommendations on how to fix this, and if you think using verilog2oa and conn2sch could be an alternative to importing verilog in CIW. Thank you very much!

    Wonyoung
Reply
  • At the same time, I am trying to see if using "verilog2oa" and "conn2sch" can import verilog to Cadence schematic using the following commands.

    verilog2oa -verilog "./myverilog.syn.v" -top "myverilog" -lib "test" -view "netlist" -tieHigh VDD -tieLow VSS -overwrite

    conn2sch -lib test -cell myverilog -view netlist -destlib test -destview schematic -verbose -param conn2sch.conf

    When I run conn2sch, it complains that "ERROR (CONN2SCH-193): Instance XXX is not bound to any master.". I was wondering if you have any recommendations on how to fix this, and if you think using verilog2oa and conn2sch could be an alternative to importing verilog in CIW. Thank you very much!

    Wonyoung
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.